参数资料
| 型号： | PCF8562TT/S400/2,1 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 19/43页 |
| 文件大小： | 0K |
| 描述： | IC LCD DRIVER 48-TSSOP |
| 标准包装： | 2,000 |
| 显示器类型： | LCD |
| 配置： | 7段 + DP，14段 + DP + AP，点阵 |
| 接口： | I²C，2 线串口 |
| 数字或字符： | 8 个字符，16 个字符 |
| 电流 - 电源： | 8µA |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | PCF8562TTS40021 |
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NXP Semiconductors
PCF8562
Universal LCD driver for low multiplex rates
? In static drive mode the eight transmitted data bits are placed in row 0 as one byte.
? In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
? In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.10.3 ).
? In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
7.10.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 12 ). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
?
?
?
?
In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
If an I 2 C-bus data access is terminated early then the state of the data pointer is unknown.
The data pointer should be re-written prior to further RAM accesses.
7.10.2 Subaddress counter
The storage of display data is determined by the content of the subaddress counter.
Storage is allowed to take place only when the content of the subaddress counter
matches with the hardware subaddress applied to A0, A1, and A2. The subaddress
counter value is defined by the device-select command (see Table 13 ). If the content of
the subaddress counter and the hardware subaddress do not match then data storage is
inhibited but the data pointer is incremented as if data storage had taken place. The
subaddress counter is also incremented when the data pointer overflows.
The hardware subaddress must not be changed while the device is being accessed on the
I 2 C-bus interface.
PCF8562
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 June 2011
? NXP B.V. 2011. All rights reserved.
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| PCF8563 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Real-time clock/calendar |
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| PCF8563BS/4,118 | 功能描述:实时时钟 ULTRA LOW POWER RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
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