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参数资料
| 型号： | PCF8890 |
| 英文描述： | 240 + 1 outputs TFT LCD gate driver |
| 中文描述： | 240 1输出TFT液晶栅极驱动器 |
| 文件页数： | 23/76页 |
| 文件大小： | 385K |
| 代理商： | PCF8890 |
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2002 Aug 16
23
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
8
INSTRUCTIONS
The PCF8832 communicates with the host via two 8-bit
parallel interfaces, a 3-line or a 4-line serial peripheral
interface or an I
2
C-bus interface. Processing of the
instructions does not require the display clock.
The PCF8832 has two access types, those defining the
operating mode of the device (instructions) and those
filling the display RAM. The latter are the most frequently
used. Efficient data transfer is achieved by
auto-incrementing RAM address pointers.
There are three types of instructions:
Defining display configuration
Miscellaneous instructions
Setting X and Y-addresses.
The initial sequence to be sent to the IC is given in Table 5.
Table 5
Initial instruction sequence
CONTROL BYTE (HEX)
REGISTER VALUE (HEX)
85
A2
06
00
Table 6
Only command register addresses shown are allowed; after reset the registers go to their default value;
δ
is equivalent
to don't care; see Table 7 for explanation of control bits used
Command register
ADR
(HEX)
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
(HEX)
DESCRIPTION
00
01
02
03
04
05
06
07
08
09
0A
0
0
0
0
0
0
0
0
0
0
δ
0
0
0
0
0
δ
0
0
0
0
0
0
0
0
0
0
δ
0
0
00
01
00
00
00
02
00
7F
00
A7
07
NOP (no operation)
Power-down
RAM data addressing
data control
display settings
oscillator-related bits
X-ADR start; 0
≤
xs
≤
FF
X-ADR end; xs
≤
xe
≤
FF
Y-ADR start; 0
≤
ys
≤
A8
Y-ADR end; ys
≤
ye
≤
A8
IO configuration;
oscillator frequency
n-line inversion
mapping blue scale b00;
b01
mapping blue scale b10;
b11
colour filter (RGB array)
active area 1 start ADR
active area 1 end ADR
active area 2 start ADR
active area 2 end ADR
scroll area start ADR;
DSA1
≤
DSA2
scroll area end ADR
scroll entry point
set frame frequency
RSTA
MX
L
DIM
ER
xs[1]
xe[1]
ys[1]
ye[1]
VCOE
PD
0
V
DON
EC
xs[0]
xe[0]
ys[0]
ye[0]
OFQ
MY
δ
PM
0
xs[2]
xe[2]
ys[2]
ye[2]
VMOE
0
SPS
0
xs[3]
xe[3]
ys[3]
ye[3]
δ
xs[7]
xe[7]
ys[7]
ye[7]
δ
xs[6]
xe[6]
ys[6]
ye[6]
δ
xs[5]
xe[5]
ys[5]
ye[5]
δ
xs[4]
xe[4]
ys[4]
ye[4]
δ
0B
0C
NLI7
0
NLI6
0
NLI5
b002
NLI4
b001
NLI3
b000
NLI2
b012
NLI1
b011
NLI0
b010
00
01
0D
0
0
b102
b101
b100
b112
b111
b110
27
0E
0F
10
11
12
13
0
0
0
0
δ
0
0
CF0
00
00
4F
50
9F
00
AA1S7 AA1S6 AA1S5 AA1S4 AA1S3 AA1S2 AA1S1 AA1S0
AA1E7 AA1E6 AA1E5 AA1E4 AA1E3 AA1E2 AA1E1 AA1E0
AA2S7 AA2S6 AA2S5 AA2S4 AA2S3 AA2S2 AA2S1 AA2S0
AA2E7 AA2E6 AA2E5 AA2E4 AA2E3 AA2E2 AA2E1 AA2E0
DSA17 DSA16 DSA15 DSA14 DSA13 DSA12 DSA11 DSA10
14
15
16
DSA27 DSA26 DSA25 DSA24 DSA23 DSA22 DSA21 DSA20
SEP7
SEP6
SEP5
SEP4
0
0
δ
FFQ4
00
00
05
SEP3
FFQ3
SEP2
FFQ2
SEP1
FFQ1
SEP0
FFQ0
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