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| 型号： | PCF8890 |
| 英文描述： | 240 + 1 outputs TFT LCD gate driver |
| 中文描述： | 240 1输出TFT液晶栅极驱动器 |
| 文件页数： | 47/76页 |
| 文件大小： | 385K |
| 代理商： | PCF8890 |
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2002 Aug 16
47
Philips Semiconductors
Preliminary specification
STN RGB - 384 output column driver
PCF8832
12.1.3
S
TART AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy (see Fig.48). A HIGH-to-LOW transition of the data line,
while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
handbook, full pagewidth
MBC622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
Fig.48 Definition of start and stop conditions.
12.1.4
A
CKNOWLEDGE
Each byte of eight bits is followed by an acknowledge bit
(see Fig.49). The acknowledge bit is a HIGH signal put on
the bus by the transmitter during which time the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal an end of data to the transmitter by not generating
an acknowledge on the last byte that has been clocked out
of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop
condition.
handbook, full pagewidth
MBC602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
Fig.49 Acknowledge on the I
2
C-bus.
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