参数资料
型号: PCX7447AVGH1000NB
厂商: Atmel
文件页数: 20/52页
文件大小: 0K
描述: IC MPU 32BIT 1000MHZ 360CBGA
标准包装: 44
处理器类型: PowerPC 32-位 RISC
速度: 1.0GHz
电压: 1.1V
安装类型: 表面贴装
封装/外壳: 360-CBBGA 裸露焊盘
供应商设备封装: 360-CBGA(25x25)
包装: 托盘
27
0833E–HIREL–01/07
e2v semiconductors SAS 2007
PC7447A
9.2.2
Processor Bus AC Specifications
Table 9-3 provides the processor bus AC timing specifications for the PC7447A as defined in Figure 7-2
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-
nal in question. All output timings assume a purely resistive 50
load (see Figure 7-2 on page 20). Input and output timings
are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
Table 9-3.
Processor Bus AC Timing Specifications
(1) (at Recommended Operating Conditions, see Table 6-2 on page
Symbol(2)
Parameter
All Speed Grades
Unit
Min
Max
tAVKH
tDVKH
t
IVKH
t
Input setup times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS,
EXT_QUAL, PMON_IN, SHD[0:1],
BMODE[0:1], BVSEL
1.8
ns
t
AXKH
tDXKH
tIXKH
Input hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BG, CKSTP_IN, DBG, DTI[0:3], GBL,
TT[0:3], QACK, TA, TBEN, TEA, TS, EXT_QUAL,
PMON_IN, SHD[0:1]
BMODE[0:1], BVSEL
0
ns
t
KHAV
t
KHDV
tKHOV
Output valid times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],
GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT
2
ns
t
KHAX
tKHDX
t
KHOX
Output hold times:
A[0:35], AP[0:4]
D[0:63], DP[0:7]
AACK, ARTRY, BR, CI, CKSTP_IN, DRDY, DTI[0:3],
GBL, HIT, PMON_OUT, QREQ, TBST, TSIZ[0:2], TT[0:3],
TS, SHD[0:1], WT
0.5
ns
t
KHOE
SYSCLK to output enable
0.5
ns
t
KHOZ
SYSCLK to output high impedance (all except TS, ARTRY, SHD0,
SHD1)
–3.5
ns
t
KHTSPZ
SYSCLK to TS high impedance after precharge
1
t
SYSCLK
tKHARP
Maximum delay to ARTRY/SHD0/SHD1 precharge
1
tSYSCLK
t
SYSCLK to ARTRY/SHD0/SHD1 high impedance after precharge
2
t
SYSCLK
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