![](http://datasheet.mmic.net.cn/Atmel/PCX7447AVGH1167NB_datasheet_99284/PCX7447AVGH1167NB_5.png)
5
0833E–HIREL–01/07
e2v semiconductors SAS 2007
PC7447A
Rename buffers
– 16 GPR rename buffers
– 16 FPR rename buffers
– 16 VR rename buffers
Dispatch unit
– Decode/dispatch stage fully decodes each instruction
Completion unit
– The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending
– Guarantees sequential programming model (precise exception model)
– Monitors all dispatched instructions and retires them in order
– Tracks unresolved branches and flushes instructions after a mispredicted branch
– Retires as many as three instructions per clock cycle
Separate on-chip L1 instruction and data caches (Harvard Architecture)
– 32-Kbyte, eight-way set-associative instruction and data caches
– Pseudo least-recently-used (PLRU) replacement algorithm
– 32-byte (eight-word) L1 cache block
– Physically indexed/physical tags
– Cache write-back or write-through operation programmable on a per-page or per-block basis
– Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycle
– Caches can be disabled in software
– Caches can be locked in software
– MESI data cache coherency maintained in hardware
– Separate copy of data cache tags for efficient snooping
– Parity support on cache and tags
– No snooping of instruction cache except for icbi instruction
– Data cache supports AltiVec LRU and transient instructions
– Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
Level 2 (L2) cache interface
– On-chip, 512-Kbyte, eight-way set-associative unified instruction and data cache
– Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
– A total nine-cycle load latency for an L1 data cache miss that hits in L2
– Cache write-back or write-through operation programmable on a per-page or per-block basis
64-byte, two-sectored line size
– Parity support on cache
Separate memory management units (MMUs) for instructions and data
– 52-bit virtual address, 32- or 36-bit physical address