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| 型号： | PH28F128L18T85 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | StrataFlash Wireless Memory |
| 中文描述： | 8M X 16 FLASH 1.8V PROM, 85 ns, PBGA56 |
| 封装： | 0.75 MM PITCH, LEAD FREE, VFBGA-56 |
| 文件页数： | 48/106页 |
| 文件大小： | 1272K |
| 代理商： | PH28F128L18T85 |
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Intel StrataFlash Wireless Memory (L18)
April 2005
48
Intel StrataFlash Wireless Memory (L18)
Order Number: 251902, Revision: 009
Datasheet
9.3
Command Definitions
Valid device command codes and descriptions are shown in
Table 9
.
Protection
Program Protection Register
2
Write
PRA
0xC0
Write
PRA
PD
Program Lock Register
2
Write
LRA
0xC0
Write
LRA
LRD
Configuration
Program Read Configuration Register
2
Write
RCD
0x60
Write
RCD
0x03
Notes:
1.
First command cycle address should be the same as the operation’s target address.
PnA = Address within the partition.
PBA = Partition base address.
IA = Identification code address offset.
QA = CFI Query address offset.
BA = Address within the block.
WA = Word address of memory location to be written.
PRA = Protection Register address.
LRA = Lock Register address.
X = Any valid address within the device.
ID = Identifier data.
QD = Query data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
PD = Protection Register data.
PD = Protection Register data.
LRD = Lock Register data.
RCD = Read Configuration Register data on A[15:0]. A[MAX:16] can select any partition
.
The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming
operation.
The confirm command (0xD0) is followed by the buffer data.
2.
3.
4.
Table 8.
Command Bus Cycles (Sheet 2 of 2)
Mode
Command
Bus
Cycles
First Bus Cycle
Second Bus Cycle
Oper
Addr
1
Data
2
Oper
Addr
1
Data
2
Table 9.
Command Codes and Definitions (Sheet 1 of 2)
Mode
Code Device Mode
0xFF Read Array
Description
Read
Places the addressed partition in Read Array mode. Array data is output on DQ[15:0].
Places the addressed partition in Read Status Register mode. The partition enters this
mode after a program or erase command is issued. Status Register data is output on
DQ[7:0].
0x70Register
0x90
Read Device
ID or
Configuration
Register
Places the addressed partition in Read Device Identifier mode. Subsequent reads from
addresses within the partition outputs manufacturer/device codes, Configuration Register
data, Block Lock status, or Protection Register data on DQ[15:0].
0x98 Read Query
Places the addressed partition in Read Query mode. Subsequent reads from the partition
addresses output Common Flash Interface information on DQ[7:0].
The WSM can only set Status Register error bits. The Clear Status Register command is
used to clear the SR error bits.
0x50Register
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相关代理商/技术参数 |
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|---|---|
| PH28F128W18BD60A | 制造商:Micron Technology Inc 功能描述:NOR Flash Parallel 1.8V 128Mbit 8M x 16bit 60ns 56-Pin VFBGA Tray |
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