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参数资料
型号： PIC12F683-E/MD
厂商： Microchip Technology
文件页数： 157/176页
文件大小： 0K
描述： IC PIC MCU FLASH 2KX14 8DFN
产品培训模块： Asynchronous Stimulus
Digi-Key 应用说明： AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
标准包装： 91
系列： PIC® 12F
核心处理器： PIC
芯体尺寸： 8-位
速度： 20MHz
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 5
程序存储器容量： 3.5KB（2K x 14）
程序存储器类型： 闪存
EEPROM 大小： 256 x 8
RAM 容量： 128 x 8
电压 - 电源 (Vcc/Vdd)： 2 V ~ 5.5 V
数据转换器： A/D 4x10b
振荡器型： 内部
工作温度： -40°C ~ 125°C
封装/外壳： 8-VDFN 裸露焊盘
包装： 管件
配用： AC164326-ND - MODULA SKT PM3 20QFN
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
2007 Microchip Technology Inc.
DS41211D-page 79
PIC12F683
11.3.1
PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 11-1.
EQUATION 11-1:
PWM PERIOD
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
TMR2 is cleared
The CCP1 pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
The PWM duty cycle is latched from CCPR1L into
CCPR1H.
11.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR1L register and
DC1B<1:0> bits of the CCP1CON register. The
CCPR1L contains the eight MSbs and the CCP1<1:0>
bits of the CCP1CON register contain the two LSbs.
CCPR1L and DC1B<1:0> bits of the CCP1CON
register can be written to at any time. The duty cycle
value is not latched into CCPR1H until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR1H
register is read-only.
Equation 11-2 is used to calculate the PWM pulse
width.
Equation 11-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 11-2:
PULSE WIDTH
EQUATION 11-3:
DUTY CYCLE RATIO
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPR1H and 2-
bit latch, then the CCP1 pin is cleared (see Figure 11-1).
11.3.3
PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 11-4.
EQUATION 11-4:
PWM RESOLUTION
TABLE 11-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
TABLE 11-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
Note:
The Timer2 postscaler (see Section 7.0
“Timer2 Module”) is not used in the
determination of the PWM frequency.
PWM Period
PR2
() 1
+
[] 4TOSC
=
(TMR2 Prescale Value)
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
Pulse Width
CCPR1L:CCP1CON<5:4>
()
=
TOSC
(TMR2 Prescale Value)
Duty Cycle Ratio
CCPR1L:CCP1CON<5:4>
()
4PR2
1
+
()
-----------------------------------------------------------------------
=
Resolution
4PR2
1
+
()
[]
log
2
()
log
------------------------------------------ bits
=
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
16
4
1
PR2 Value
0xFF
0x3F
0x1F
0x17
Maximum Resolution (bits)
10
8
7
6.6
PWM Frequency
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
Timer Prescale (1, 4, 16)
16
4
1
PR2 Value
0x65
0x19
0x0C
0x09
Maximum Resolution (bits)
8
6
5
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