参数资料
型号: PIC12F683-E/MD
厂商: Microchip Technology
文件页数: 158/176页
文件大小: 0K
描述: IC PIC MCU FLASH 2KX14 8DFN
产品培训模块: Asynchronous Stimulus
Digi-Key 应用说明: AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
标准包装: 91
系列: PIC® 12F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 5
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 8-VDFN 裸露焊盘
包装: 管件
配用: AC164326-ND - MODULA SKT PM3 20QFN
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
PIC12F683
DS41211D-page 80
2007 Microchip Technology Inc.
11.3.4
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCP1
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
11.3.5
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Clock Monitor)” for additional details.
11.3.6
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
11.3.7
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
Disable the PWM pin (CCP1) output drivers by
setting the associated TRIS bit.
2.
Set the PWM period by loading the PR2 register.
3.
Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
4.
Set the PWM duty cycle by loading the CCPR1L
register and DC1B bits of the CCP1CON register.
5.
Configure and start Timer2:
Clear the TMR2IF interrupt flag bit of the
PIR1 register.
Set the Timer2 prescale value by loading the
T2CKPS bits of the T2CON register.
Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6.
Enable PWM output after a new PWM cycle has
started:
Wait until Timer2 overflows (TMR2IF bit of
the PIR1 register is set).
Enable the CCP1 pin output driver by
clearing the associated TRIS bit.
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