参数资料
型号: PIC18F252-E/SO
厂商: Microchip Technology
文件页数: 90/134页
文件大小: 0K
描述: IC MCU CMOS 40MHZ 16K FLSH28SOIC
产品培训模块: Asynchronous Stimulus
标准包装: 27
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 23
程序存储器容量: 32KB(16K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 1.5K x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 5x10b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
1997 Microchip Technology Inc.
DS30444E - page 59
PIC16C9XX
10.2.1
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
10.2.2
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is gen-
erated (if enabled).
10.2.3
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion. This
allows the CCPR1H:CCPR1L register pair to effectively
be a 16-bit programmable period register for Timer1.
10.3
PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 10-4 shows a simplied block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 10.3.3.
Note:
The "special event trigger" from the CCP1
module will not set interrupt ag bit
TMR1IF (PIR1<0>).
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
FIGURE 10-4: SIMPLIFIED PWM BLOCK
DIAGRAM
A PWM output (Figure 10-5) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 10-5: PWM OUTPUT
10.3.1
PWM PERIOD
The PWM period is specied by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM period = [ (PR2) + 1 ] 4 TOSC
(TMR2 prescale value)
PWM frequency is dened as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
TMR2 is cleared
The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
The PWM duty cycle is latched from CCPR1L into
CCPR1H
CCPR1L
CCPR1H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R
Q
S
Duty cycle registers
CCP1CON<5:4>
Clear Timer,
CCP1 pin and
latch D.C.
TRISC<2>
RC1/CCP1
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
Period
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
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