
5: PINS
1-14
EPSON
S1D13505F00A HARDWARE FUNCTIONAL
SPECIFICATION (X23A-A-001-12)
AB20
I
111
C
Hi-Z
For the MIPS/ISA Bus, this pin inputs system address bit 20. Note that
for the ISA Bus, the unlatched LA20 must rst be latched before input to
AB20.
For Philips PR31500/31700 Bus, this pin inputs the address latch enable
(ALE).
For Toshiba TX3912 Bus, this pin inputs the address latch enable (ALE).
For PowerPC Bus, this pin inputs the system address bit 11 (A11).
For all other busses, this pin inputs the system address bit 20 (A20).
See “Table 5-7 CPU Interface Pin Mapping” for summary. See the respec-
tive AC Timing diagram for detailed functionality.
DB[15:0]
IO
16–31
C/TS2
Hi-Z
These pins are the system data bus. For 8-bit bus modes, unused data pins
should be tied to VDD.
For SH-3/SH-4 Bus, these pins are connected to D[15:0].
For MC68K Bus 1, these pins are connected to D[15:0].
For MC68K Bus 2, these pins are connected to D[31:16] for 32-bit
devices (e.g. MC68030) or D[15:0] for 16-bit devices (e.g. MC68340).
For Generic Bus, these pins are connected to D[15:0].
For MIPS/ISA Bus, these pins are connected to SD[15:0].
For Philips PR31500/31700 Bus, these pins are connected to D[31:16].
For Toshiba TX3912 Bus, pins [15:8] are connected to D[23:16] and
pins [7:0] are connected to D[31:24].
For PowerPC Bus, these pins are connected to D[0:15].
For PC Card (PCMCIA) Bus, these pins are connected to D[15:0].
See “Table 5-7 CPU Interface Pin Mapping” for summary. See the respec-
tive AC Timing diagram for detailed functionality.
WE1#
IO
9
CS/TS2
Hi-Z
This is a multi-purpose pin:
For SH-3/SH-4 Bus, this pin inputs the write enable signal for the upper
data byte (WE1#).
For MC68K Bus 1, this pin inputs the upper data strobe (UDS#).
For MC68K Bus 2, this pin inputs the data strobe (DS#).
For Generic Bus, this pin inputs the write enable signal for the upper
data byte (WE1#).
For MIPS/ISA Bus, this pin inputs the system byte high enable signal
(SBHE#).
For Philips PR31500/31700 Bus, this pin inputs the odd byte access
enable signal (/CARDxCSH).
For Toshiba TX3912 Bus, this pin inputs the odd byte access enable sig-
nal (CARDxCSH*).
For PowerPC Bus, this pin outputs the burst inhibit signal (BI#).
For PC Card (PCMCIA) Bus, this pin inputs the card enable 2 signal
(-CE2).
See “Table 5-7 CPU Interface Pin Mapping” for summary. See the respec-
tive AC Timing diagram for detailed functionality.
M/R#
I
5
C
Hi-Z
For Philips PR31500/31700 Bus, this pin is connected to VDD.
For Toshiba TX3912 Bus, this pin is connected to VDD.
For all busses, this input pin is used to select between the display buffer
and register address spaces of the S1D13505. M/R# is set high to access
the display buffer and low to access the registers. See Register Mapping.
See “Table 5-7 CPU Interface Pin Mapping” on page 1-20.
CS#
I
4
C
Hi-Z
For Philips PR31500/31700 Bus, this pin is connected to VDD.
For Toshiba TX3912 Bus, this pin is connected to VDD.
For all busses, this is the Chip Select input.
See “Table 5-7 CPU Interface Pin Mapping” on page 1-20. See the respec-
tive AC Timing diagram for detailed functionality.
Table 5-1 Host Interface Pin Descriptions
Pin Name
Type
Pin #
Driver
Reset#
State
Description