
5: PINS
S1D13505F00A HARDWARE FUNCTIONAL
EPSON
1-15
SPECIFICATION (X23A-A-001-12)
BUSCLK
I
13
C
Hi-Z
This pin inputs the system bus clock. It is possible to apply a 2x clock and
divide it by 2 internally - see MD12 in Summary of Conguration
Options.
For SH-3/SH-4 Bus, this pin is connected to CKIO.
For MC68K Bus 1, this pin is connected to CLK.
For MC68K Bus 2, this pin is connected to CLK.
For Generic Bus, this pin is connected to BCLK.
For MIPS/ISA Bus, this pin is connected to CLK.
For Philips PR31500/31700 Bus, this pin is connected to DCLKOUT.
For Toshiba TX3912 Bus, this pin is connected to DCLKOUT.
For PowerPC Bus, this pin is connected to CLKOUT.
For PC Card (PCMCIA) Bus, this pin is connected to the input clock
(CLKI, pin 69).
See “Table 5-7 CPU Interface Pin Mapping” for summary. See the respec-
tive AC Timing diagram for detailed functionality.
BS#
I
6
CS
Hi-Z
This is a multi-purpose pin:
For SH-3/SH-4 Bus, this pin inputs the bus start signal (BS#).
For MC68K Bus 1, this pin inputs the address strobe (AS#).
For MC68K Bus 2, this pin inputs the address strobe (AS#).
For Generic Bus, this pin is connected to VDD.
For MIPS/ISA Bus, this pin is connected to VDD.
For Philips PR31500/31700 Bus, this pin is connected to VDD.
For Toshiba TX3912 Bus, this pin is connected to VDD.
For PowerPC Bus, this pin inputs the Transfer Start signal (TS#).
For PC Card (PCMCIA) Bus, this pin is connected to VDD.
See “Table 5-7 CPU Interface Pin Mapping” for summary. See the respec-
tive AC Timing diagram for detailed functionality.
RD/WR#
I
10
CS
Hi-Z
This is a multi-purpose pin:
For SH-3/SH-4 Bus, this pin inputs the read write signal (RD/WR#). The
S1D13505 needs this signal for early decode of the bus cycle.
For MC68K Bus 1, this pin inputs the read write signal (R/W#).
For MC68K Bus 2, this pin inputs the read write signal (R/W#).
For Generic Bus, this pin inputs the read command for the upper data
byte (RD1#).
For MIPS/ISA Bus, this pin is connected to VDD.
For Philips PR31500/31700 Bus, this pin inputs the even byte access
enable signal (/CARDxCSL).
For Toshiba TX3912 Bus, this pin inputs the even byte access enable sig-
nal (CARDxCSL*).
For PowerPC Bus, this pin inputs the read write signal (RD/WR#).
For PC Card (PCMCIA) Bus, this pin inputs the card enable 1 signal
(-CE1).
See “Table 5-7 CPU Interface Pin Mapping” for summary. See the respec-
tive AC Timing diagram for detailed functionality.
RD#
I
7
CS
Hi-Z
This is a multi-purpose pin:
For SH-3/SH-4 Bus, this pin inputs the read signal (RD#).
For MC68K Bus 1, this pin is connected to VDD.
For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1).
For Generic Bus, this pin inputs the read command for the lower data
byte (RD0#).
For MIPS/ISA Bus, this pin inputs the memory read signal (MEMR#).
For Philips PR31500/31700 Bus, this pin inputs the memory read com-
mand (/RD).
For Toshiba TX3912 Bus, this pin inputs the memory read command
(RD*).
For PowerPC Bus, this pin inputs the transfer size 0 signal (TSIZ0).
For PC Card (PCMCIA) Bus, this pin inputs the output enable signal (-OE).
See “Table 5-7 CPU Interface Pin Mapping” for summary. See the respec-
tive AC Timing diagram for detailed functionality.
Table 5-1 Host Interface Pin Descriptions
Pin Name
Type
Pin #
Driver
Reset#
State
Description