![](http://datasheet.mmic.net.cn/140000/S1D13806F00A_datasheet_5011559/S1D13806F00A_23.png)
4: PINS
S1D13806 SERIES HARDWARE FUNCTIONAL
EPSON
1-11
SPECIFICATION (X28B-A-001-03)
DB[15:0]
IO
40-55 C/TS2
Hi-Z
These pins are the system data bus.
For SH-3/SH-4 Bus, these pins are connected to D[15:0].
For MC68K Bus 1, these pins are connected to D[15:0].
For MC68K Bus 2, these pins are connected to D[31:16] for 32-bit devices
(e.g. MC68030) or D[15:0] for 16-bit devices (e.g. MC68340).
For Generic Bus, these pins are connected to D[15:0].
For MIPS/ISA Bus, these pins are connected to SD[15:0].
For Philips PR31500/31700 Bus, pins DB[15:8] are connected to D[23:16] and
pins DB[7:0] are connected to D[31:24].
For Toshiba TX39xx Bus, pins DB[15:8] are connected to D[23:16] and pins
DB[7:0] are connected to D[31:24].
For PowerPC Bus, these pins are connected to D[0:15].
For PC Card (PCMCIA) Bus, these pins are connected to D[15:0].
See the respective AC Timing diagram for detailed functionality.
WE1#
IO
33
CS/
TS2
Hi-Z
This is a multi-purpose pin:
For SH-3/SH-4 Bus, this pin inputs the write enable signal for the upper data byte
(WE1#).
For MC68K Bus 1, this pin inputs the upper data strobe (UDS#).
For MC68K Bus 2, this pin inputs the data strobe (DS#).
For Generic Bus, this pin inputs the write enable signal for the upper data byte
(WE1#).
For MIPS/ISA Bus, this pin inputs the system byte high enable signal (SBHE#).
For Philips PR31500/31700 Bus, this pin inputs the odd byte access enable signal
(/CARDxCSH).
For Toshiba TX39xx Bus, this pin inputs the odd byte access enable signal
(CARDxCSH*).
For PowerPC Bus, this pin outputs the burst inhibit signal (BI#).
For PC Card (PCMCIA) Bus, this pin inputs the card enable 2 signal (-CE2).
See the respective AC Timing diagram for detailed functionality.
M/R#
I
29
C
Hi-Z
For Philips PR31500/31700 Bus, this pin is connected to VDD.
For Toshiba TX39xx Bus, this pin is connected to VDD.
For all other busses, this input pin is used to select between the display buffer and
register address spaces of the S1D13806. M/R# is set high to access the display
buffer and low to access the registers. See Register Mapping.
CS#
I
28
C
Hi-Z
For Philips PR31500/31700 Bus, this pin is connected to VDD.
For Toshiba TX39xx Bus, this pin is connected to VDD.
For all other busses, this is the Chip Select input.
See the respective AC Timing diagram for detailed functionality.
BUSCLK
I
60
C
Hi-Z
This pin inputs the system bus clock. It is possible to apply a 2x clock and divide it
by 2 internally - see CONF5 in Summary of Configuration Options.
For SH-3/SH-4 Bus, this pin is connected to CKIO.
For MC68K Bus 1, this pin is connected to CLK.
For MC68K Bus 2, this pin is connected to CLK.
For Generic Bus, this pin is connected to BCLK.
For MIPS/ISA Bus, this pin is connected to CLK.
For Philips PR31500/31700 Bus, this pin is connected to DCLKOUT.
For Toshiba TX39xx Bus, this pin is connected to DCLKOUT.
For PowerPC Bus, this pin is connected to CLKOUT.
For PC Card (PCMCIA) Bus, this pin is connected to the input clock
(CLKI, pin 69).
See the respective AC Timing diagram for detailed functionality.
Table 4-1 Host Interface Pin Descriptions (Continued)
Pin Name Type
Pin #
Cell
RESET#
State
Description