参数资料
型号: S75PL127JCDBFWB0
厂商: Spansion Inc.
英文描述: Power supply woltage of 2.7 to 3.1 volt
中文描述: 功率2月7号至三月一日伏的电源woltage
文件页数: 159/183页
文件大小: 4247K
代理商: S75PL127JCDBFWB0
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页当前第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页
78
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
Advance
Info rmation
General Description
The S29GL512/256/128N family of devices are 3.0V single power flash memory
manufactured using 110 nm MirrorBit technology. The S29GL512N is a 512 Mbit,
organized as 33,554,432 words or 67,108,864 bytes. The S29GL256N is a 256
Mbit, organized as 16,777,216 words or 33,554,432 bytes. The S29GL128N is a
128 Mbit, organized as 8,388,608 words or 16,777,216 bytes. The device can be
programmed either in the host system or in standard EPROM programmers.
Access times as fast as 90 ns (S29GL128N, S29GL256N, S29GL512N) are avail-
able. Note that each access time has a specific operating voltage range (VCC) and
an I/O voltage range (VIO), as specified in the “Product Selector Guide” section.
The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each
device has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and
write functions. In addition to a VCC input, a high-voltage accelerated program
(WP#/ACC) input provides shorter programming times through increased cur-
rent. This feature is intended to facilitate factory throughput during system
production, but may also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC single-
power-supply Flash standard. Commands are written to the device using
standard microprocessor write timing. Write cycles also internally latch addresses
and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through command sequences.
Once a program or erase operation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy#
(RY/BY#) output to determine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces command sequence overhead
by requiring only two write cycles to program data instead of four.
The Enhanced VersatileI/O (VIO) control allows the host system to set the
voltage levels that the device generates and tolerates on all input levels (address,
chip control, and DQ input levels) to the same voltage level that is asserted on
the VIO pin. This allows the device to operate in a 1.8 V or 3 V system environ-
ment as required.
Hardware data protection measures include a low VCC detector that automat-
ically inhibits write operations during power transitions. Persistent Sector
Protection provides in-system, command-enabled protection of any combina-
tion of sectors using a single power supply at VCC. Password Sector Protection
prevents unauthorized write and erase operations in any combination of sectors
through a user-defined 64-bit password.
The Erase Suspend/Erase Resume feature allows the host system to pause an
erase operation in a given sector to read or program any other sector and then
complete the erase operation. The Program Suspend/Program Resume fea-
ture enables the host system to pause a program operation in a given sector to
read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the
device, after which it is then ready for a new operation. The RESET# pin may be
相关PDF资料
PDF描述
S75PL127JCDBFWB2 Power supply woltage of 2.7 to 3.1 volt
S75PL127JCEBFWB2 Power supply woltage of 2.7 to 3.1 volt
S75PL127JCDBFWB3 Power supply woltage of 2.7 to 3.1 volt
S75PL127JCEBFWB3 Power supply woltage of 2.7 to 3.1 volt
S29CD016G0PFAN010 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
相关代理商/技术参数
参数描述
S75PL127JCDBFWB2 制造商:SPANSION 制造商全称:SPANSION 功能描述:Power supply woltage of 2.7 to 3.1 volt
S75PL127JCDBFWB3 制造商:SPANSION 制造商全称:SPANSION 功能描述:Power supply woltage of 2.7 to 3.1 volt
S75PL127JCDBFWU0 制造商:SPANSION 制造商全称:SPANSION 功能描述:Power supply woltage of 2.7 to 3.1 volt
S75PL127JCDBFWU2 制造商:SPANSION 制造商全称:SPANSION 功能描述:Power supply woltage of 2.7 to 3.1 volt
S75PL127JCDBFWU3 制造商:SPANSION 制造商全称:SPANSION 功能描述:Power supply woltage of 2.7 to 3.1 volt