参数资料
型号: SC28C94A1N,112
厂商: NXP Semiconductors
文件页数: 19/39页
文件大小: 0K
描述: IC UART QUAD W/FIFO 48-DIP
标准包装: 7
特点: 故障启动位检测
通道数: 4,QUART
FIFO's: 8 字节
电源电压: 5V
带自动流量控制功能:
带故障启动位检测功能:
带调制解调器控制功能:
带CMOS:
安装类型: 通孔
封装/外壳: 48-DIP(0.600",15.24mm)
供应商设备封装: 48-DIP
包装: 管件
其它名称: 568-1115-5
935262535112
SC28C94A1N
Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
26
AC ELECTRICAL CHARACTERISTICS1
VCC = 5 V ± 10 %, TA = –40 _C to 85 _C, unless otherwise specified.
NO
FIGURE
CHARACTERISTIC
LIMITS
UNIT
NO.
FIGURE
CHARACTERISTIC
Min
Typ
Max
UNIT
1
4
A[5:0] Setup time to RDN WRN Low
0
ns
2
4
A[5:0] Hold time from RDN WRN Low
45
ns
3
4
CEN Setup time to RDN WRN Low2
0
ns
4
CEN Hold time from RDN WRN High2
0
ns
5
4
RDN WRN Pulse Width Low
65
ns
6
4
D[7:0] Data Valid after CEN and RDN Low
65
ns
7
4
D[7:0] Data Bus floating after RDN or CEN High
10
ns
8
4
D[7:0] Data Bus Setup time before WRN or CEN High
5
ns
9
4
D[7:0] Hold time after WRN or CEN High
0
ns
10
4
Time between Reads and/or Writes3
20
ns
NOTES:
1. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
supply range.
2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as a ‘strobing’ input. CEN and
RDN (also CEN and WRN) are ANDed internally. As a consequence the signal asserted last initiates the cycle; the signal negated first
terminates the cycle. Address is latched at leading edge of a read or write cycle.
3. The RDN signal must be negated for this time to guarantee that internal registers update before the next read.
A[5:0]
CEN
RDN
WRN
D[7:0]
12
1
2
10
5
7
READ CYCLE
WRITE CYCLE
3
5
6
4
8
9
SD00164
Figure 4. A Read Cycle Followed by a Write Cycle without DACKN
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