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参数资料
| 型号： | SC28C94A1N,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 5/39页 |
| 文件大小： | 0K |
| 描述： | IC UART QUAD W/FIFO 48-DIP |
| 标准包装： | 7 |
| 特点： | 故障启动位检测 |
| 通道数： | 4，QUART |
| FIFO's： | 8 字节 |
| 电源电压： | 5V |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 48-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 48-DIP |
| 包装： | 管件 |
| 其它名称： | 568-1115-5 935262535112 SC28C94A1N |
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Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
13
Vectored Interrupts
The QUART responds to an Interrupt Acknowledge (IACK) initiated
by the host by providing an Interrupt Acknowledge Vector on D7:0.
The interrupt acknowledge cycle is terminated with a DACKN pulse.
The vector provided by the QUART can have one of the three forms
under control of the IVC control field (bits 1:0 of the Interrupt Control
Register):
With IVC = 00 (IVR only)
IVR7:0
8
With IVC = 01 (channel number)
IVR7:2
6
Chan #
2
With IVC = 10 (type & channel number)
IVR7:5
3
Chan #
2
Type
3
SD00163
A code of 11 in the Interrupt Vector Control Field of the ICR results
in NO interrupt vector being generated. The external data bus is
driven to a high impedance throughout the IACK cycle. A DACKN
will be generated normally for the IACK cycle, however.
NOTE: If IACKN is not being used then the command “UPDATE
CIR” must be issued for the global and interrupt registers to be
updated.
PROGRAMMING UART CONTROL REGISTERS
The operation of the QUART is programmed by writing control
words into the appropriate registers. Operational feedback is
provided via status registers which can be read by the CPU.
Addressing of the registers is described in Table 1.
The bit formats of the QUART registers are depicted in Table 2.
Table 4.
Register Bit Formats, Duart ab. [duplicated for Duart cd]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MR0 (Mode Register 0)
Rx Watchdog
Timer
RxINT2 bit
TxINT Control
These bits not implemented.
They should be considered Reserved.
0 = off
1 = on
These bits should normally be set to 0
x
MR1 (Mode Register 1)
RxRTS
Control
RxINT1 Select
Error Mode*
Parity Mode
Parity Type
Bits per Character
0 = No
1 = Yes
Normally set to 0
0 = Char
1 = Block
00 = With parity
01 = Force parity
10 = No parity
11 = Wake-up mode
0 = Even
1 = Odd
00 = 5
01 = 6
10 = 7
11 = 8
NOTE: *In block error mode, block error conditions must be cleared by using the error reset command (command 4x) or a receiver reset.
MR2 (Mode Register 2)
Channel Mode
TxRTS
Control
CTS Enable Tx
Stop Bit Length*
00 = Normal
01 = Auto-echo
10 = Local loop
11 = Remote loop
0 = No
1 = Yes
0 = No
1 = Yes
0 = 0.563 4 = 0.813 8 = 1.563 C = 1.813
1 = 0.625 5 = 0.875 9 = 1.625 C = 1.875
2 = 0.688 6 = 0.938 A = 1.688 E = 1.938
3 = 0.750 7 = 1.000 B = 1.750 F = 2.000
NOTE: Add 0.5 to values shown above for 0–7, if channel is programmed for 5 bits/char.
CSR (Clock Select Register)
Receiver Clock Select
Transmitter Clock Select
See text
CR (Command Register)
Miscellaneous Commands
Disable Tx
Enable Tx
Disable Rx
Enable Rx
See text
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
0 = No
1 = Yes
NOTE: Issuing commands contained in the upper four bits of the “Command Register” should be separated in time by at least three (3) X1
clock edges. Allow four (4) edges if the “X1 clock divide by 2” mode is used. A disabled transmitter cannot be loaded.
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