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参数资料
| 型号： | SC28C94A1N,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 28/39页 |
| 文件大小： | 0K |
| 描述： | IC UART QUAD W/FIFO 48-DIP |
| 标准包装： | 7 |
| 特点： | 故障启动位检测 |
| 通道数： | 4，QUART |
| FIFO's： | 8 字节 |
| 电源电压： | 5V |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 48-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 48-DIP |
| 包装： | 管件 |
| 其它名称： | 568-1115-5 935262535112 SC28C94A1N |
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Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
34
INTERRUPT NOTES
The following is a brief description of the new QUART “Bidding”
interrupt system, interrupt vector and the use of the Global registers.
The new features of the QUARTs have been developed to greatly
reduce the microprocessor time required to service uart interrupts.
Bus cycle times have also been enhanced. By use of the new
Current Interrupt Register (CIR) the speed of a polled system is
also improved. For example programming the SCC2692 to interrupt
on TxRDY and RxFUL would generate four interrupts for every six
characters processed along with at least two additional accesses to
the chip for each interrupt. This amounts to two non–data chip
accesses per character. In the 28C94 this has been reduced to 0.25
non data accesses per character; an eight fold improvement. In
certain conditions use of the global registers will yield a greater
improvement.
The QUART has 18 possible sources which can be programmed to
generate an interrupt:
4 Receiver channels
4 Transmitter Channels
4 Received ”Break” conditions
4 Change of State Detectors (a total of 8 ports)
2 Counter/Timers
These sources are encoded in such a way that they generate a
unique value. This value is defined by chip hardwire programming,
user programming, and the source’s present condition. The values
the sources generate are compared (at the X1 clock rate) to a user
defined Interrupt Threshold value contained in the ICR (Interrupt
Control Register). When the source’s value exceeds the threshold
the interrupt is generated. It is the source’s value which is captured
in the CIR.
The heart of the interrupt speed enhancement is attained by
allowing the interrupting source to encode its channel, interrupt type
and, if appropriate, the number of FIFO bytes requiring service. This
information is coded and transferred the CIR (Current Interrupt
Register) at the time IACKN is asserted or the command ’Update
CIR’ is executed. Upon an interrupt the processor may read this
register and in one access determine the ”who, what and how
much”. This CIR value is used to drive the interrupt vector
modification (when used) and the new ”Global” registers.
“Global” Registers
The ”Global Registers” are effectively pointers which use the
contents of the CIR to direct a read or write operation to Rx or Tx or
other source which is currently interrupting. There are four global
registers defined in the register map:
1. Global Interrupting Byte Count
2. Global Interrupting Channel
3. Global Receive FIFO Register
4. Global Transmit FIFO Register
The global receive and transmit registers operate as an indirect
address. The data read from the global receive register will be that
of the currently interrupting receiver; the data written to the global
transmit register will go to the currently interrupting transmitter. The
interesting point here is that under certain circumstances an
interrupt can be serviced without an interrogation of the chip.
For completeness it should be noted that the global registers are not
physical devices. Reads of the Global Byte and Channel registers
give the Byte count or Channel number, respectively, (right justified)
of the interrupting channel. The CIR data is mapped to these
”registers”.
Table 9.
Bidding Format
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
Rx Byte count
Error
1
Channel No.
Receiver bid With error
Rx Byte count
no Error
0
1
Channel No.
Receiver bid No error
0
Tx Byte Count
1
0
Channel No.
Transmit bid
Programmable
1
0
Channel No.
Receive Break
Programmable
0
1
Channel No.
Change of State
Programmable
0
1
0
1
Channel No.
Counter/Timer
NOTES:
1. The ones and zeros above represent the hardwired positions.
2. Note the format of bits 4:2. They represent the identity of the interrupting source.
3. Bids with the highest number of contiguous MSBs win the bid.
1 1 1
Receiver with error
0 1 1
Receiver without error
x 1 0
Transmitter
1 0 0
Receiver Break detect
0 0 1
Change of State
1 0 1
Counter/Timer
0 0 0
No interrupt
In these identifiers the receivers are biased to have highest priority.
The identifier bits and the channel number bits are hardwired on the
chip. Normally the non–data interrupts would be programmed to a
low value. The programmable fields can, in some cases, make
these sources higher than a full receiver.
It would seem that a 11 programmed in the upper counter/timer bits,
for example, would cause it to interrupt nearly all the time.
This is
not true . A counter/timer that has not timed out will not bid. In a
similar fashion a receiver FIFO that is empty or a transmitter FIFO
that is full will not bid
In general terms the threshold value programmed in the ICR
(Interrupt Control Register) will reflect some fill level of the eight
character transmit and receive FIFOs that allow processor service
without underrun or overrun occurring.
Note that interrupt threshold value in the ICR is 6 bits long. This
value is aligned with the bid arbitration logic such that it bids only
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