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参数资料
| 型号： | SC28C94A1N,112 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 39/39页 |
| 文件大小： | 0K |
| 描述： | IC UART QUAD W/FIFO 48-DIP |
| 标准包装： | 7 |
| 特点： | 故障启动位检测 |
| 通道数： | 4，QUART |
| FIFO's： | 8 字节 |
| 电源电压： | 5V |
| 带自动流量控制功能： | 是 |
| 带故障启动位检测功能： | 是 |
| 带调制解调器控制功能： | 是 |
| 带CMOS： | 是 |
| 安装类型： | 通孔 |
| 封装/外壳： | 48-DIP（0.600"，15.24mm） |
| 供应商设备封装： | 48-DIP |
| 包装： | 管件 |
| 其它名称： | 568-1115-5 935262535112 SC28C94A1N |
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Philips Semiconductors
Product data sheet
SC28C94
Quad universal asynchronous receiver/transmitter (QUART)
2006 Aug 09
9
or break condition, and presents the assembled character to the
CPU via the receiver FIFO.
The receiver operates in two modes: the 1X and 16X. The 16X
mode is the more robust of the two. It allows the receiver to
establish a phase relation to the remote transmitter clock within 1/16
of a bit time and also allows validation of the start bit. The 1X mode
does not validate the start bit and assumes that the receiver clock
rising edge is centered in the data bit cell. The use of the 1X mode
implies that the transmitter clock is available to the receiver.
When operating in the 16X mode and after the receiver has been
enabled the receiver state machine will look for a high to low
transition on the RxD input. The detection of this transition will cause
the divider being driven by the 16X clock to be reset to zero and
continue counting. When the counter reaches 7 the RxD input is
sampled again and if still low a valid START BIT will be detected. If
the RxD input is high at count 7 then an invalid start bit will have
been sensed and the receiver will then look for another high to low
transition and begin validating again.
When a valid start bit is detected the receiver state machine allows
the 16X divider circuit to continue counting 0 to 15. Each time the
receiver passes count 7 (the theoretical center of the bit time)
another data bit is clocked into the receiver shift register until the
proper number of bits have been received including the parity bit, if
used, and 1/2 stop bit. After the STOP BIT is detected the receiver
state machine will wait until the next falling edge of the 1X clock and
then clock the assembled character and its status bits into the
receiver FIFO on the next rising edge of the 1X clock. The delay
from the detection of the STOP BIT to the loading of the character to
the RxFIFO will be from one half to one and one half X1 crystal
clock periods, or twice that if X1/2 is used. Receiver Status Register
bits for FIFO READY, FIFO FULL, parity error, framing error, break
detect will also set at this time. The most significant bits for data
characters less than eight bits will be set to zero.
After the stop bit is detected, the receiver will immediately look for
the next start bit. However, if a non-zero character was received
without a stop bit (i.e. framing error) and RxD remains low for
one-half of the bit period after the stop bit was sampled, then the
receiver operates as if a new start bit transition had been detected at
that point (one-half bit time after the stop bit was sampled). The
parity error, framing error and overrun error (if any) are strobed into
the SR at the received character boundary, before the RxRDY
status bit is set.
If a break condition is detected (RxD is low for the entire character
including the stop bit), only one character consisting of all zeros will
be loaded in the FIFO and the received break bit in the SR is set to
1. The “Change of Break” bit in the ISR at position 2 or 6 is also set
at this time. Note that the “Change of Break” bit will set again when
the break condition terminates. The RxD input must return to high
for two (2) clock edges of the X1 crystal clock for the receiver to
recognize the end of the break condition and begin the search for a
start bit. This will usually require a high time of one X1 clock
period or 3 X1 edges since the clock of the controller is not
synchronous to the X1 clock.
NOTE: If the RxD input is low when the receiver is enabled and
remains low for at least 9/16 of a bit time a valid start bit will be
seen and data (probably random) will be clocked into the
receiver FIFO. If the line remains low for a full character time
plus a stop bit then a break will be detected.
Receiver FIFO
The RxFIFO consists of a first-in-first-out (FIFO) with a capacity of
eight characters. Data is loaded from the receive shift register into
the top-most empty position of the FIFO. The RxRDY bit in the
status register (SR) is set whenever one or more characters are
available to be read; a FFULL status bit is set if all eight stack
positions are filled with data. The number of filled positions is
encoded into a 3-bit value. This value is sent to the interrupt bidding
logic where it is used to generate an interrupt. A read of the RxFIFO,
outputs the data at the top of the FIFO. After the read cycle, the data
FIFO and its associated status bits are ‘popped’ thus emptying a
FIFO position for new data.
NOTE: The number of filled positions in the RxFIFO is coded
as actual number filled positions. Seven filled will be coded as
7. Eight filled positions will be coded as 7
and the RxFIFO full
status bit will be set.
Status
In addition to the data word, three status bits (parity error, framing
error, and received break) are appended to each data character in
the FIFO. Status can be provided in two ways, as programmed by
the error mode control bit in the mode register. In the ‘character’
mode, status is provided on a character-by-character basis: the
status applies only to the character at the top of the FIFO. In the
‘block’ mode, the status provided in the SR for these three bits is the
logical OR of the status for all characters coming to the top of the
FIFO since the last reset error command was issued. In either
mode, reading the SR does not affect the FIFO. The FIFO is
‘popped’ only when the RxFIFO is read. Therefore, the SR should
be read prior to reading the corresponding data character.
If the FIFO is full when a new character is received, that character is
held in the receive shift register until a FIFO position is available. If
an additional character is received while this state exists, the
contents of the FIFO are not affected: the character previously in the
shift register is lost and the overrun error status bit, SR[4], will be set
upon receipt of the start bit of the new (overrunning) character.
Watchdog Timer
A “watchdog” timer is associated with each receiver. Its interrupt is
enabled by MR0[7]. The purpose of this timer is alerting the control
processor that characters are in the RxFIFO which have not been
read and/or the datastream has stopped. This situation may occur
at the end of a transmission when the last few characters received
are not sufficient to cause an interrupt.
This counter times out after 64 bit times. It is reset each time a
character is transferred from the Receive shift register to the
RxFIFO or a read of the RxFIFO is executed.
Each receiver is equipped with a watchdog timer. This timer is
enabled by MR0[7] and counts 64 RxC1X clocks. Its purpose is to
alert the controlling CPU that data is in the FIFO which has not been
read. This situation may occur at the end of a message when the
last group of characters was not long enough to cause an interrupt.
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