参数资料
型号: SCANPSC100FDMQB
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 微控制器/微处理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28
封装: CERAMIC, DIP-28
文件页数: 1/27页
文件大小: 381K
代理商: SCANPSC100FDMQB
SCANPSC100F
Embedded Boundary Scan Controller
(IEEE 1149.1 Support)
General Description
The SCANPSC100F is designed to interface a generic par-
allel processor bus to a serial scan test bus. It is useful in
improving scan throughput when applying serial vectors to
system test circuitry and reduces the software overhead that
is associated with applying serial patterns with a parallel
processor. The ’PSC100F operates by serializing data from
the parallel bus for shifting through the chain of 1149.1
compliant components (i.e., scan chain). Scan data return-
ing from the scan chain is placed on the parallel port to be
read by the host processor. Up to two scan chains can be
directly controlled with the ’PSC100F via two independent
TMS pins. Scan control is supplied with user specific pat-
terns which makes the ’PSC100F protocol-independent.
Overflow and underflow conditions are prevented by stop-
ping the test clock. A 32-bit counter is used to program the
number of TCK cycles required to complete a scan operation
within the boundary scan chain or to complete a ’PSC100F
Built-In Self Test (BIST) operation. SCANPSC100F device
drivers and 1149.1 embedded test application code are
available with National’s SCANEase software tools.
Features
n
Compatible with IEEE Std. 1149.1 (JTAG) Test Access
Port and Boundary Scan Architecture
n
Supported by National’s SCAN Ease (Embedded
Application Software Enabler) Software
n
Uses generic, asynchronous processor interface;
compatible with a wide range of processors and PCLK
frequencies
n
Directly supports up to two 1149.1 scan chains
n
16-bit Serial Signature Compaction (SSC) at the Test
Data In (TDI) port
n
Automatically produces pseudo-random patterns at the
Test Data Out (TDO) port
n
Fabricated on FACT 1.5 m CMOS process
n
Supports 1149.1 test clock (TCK) frequencies up to
25 MHz
n
TTL-compatible inputs; full-swing CMOS outputs with
24 mA source/sink capability
n
Standard Microcircuit Drawing (SMD) 5962-9475001
Connection Diagrams
28-Pin DIP and Flatpak
Pin Assignment for LCC
10032501
10032518
FACT is a trademark of Fairchild Semiconductor Corporation.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
September 1998
SCANPSC100F
Embedded
Boundary
Scan
Controller
(IEEE
1
149.1
Support)
2002 National Semiconductor Corporation
DS100325
www.national.com
相关PDF资料
PDF描述
SCANPSC100FLMQB SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28
SCB68172C2F28 VME BUS CONTROLLER, CDIP28
SCC2691AC1D24 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PDSO24
SCC2691AE1A28 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PQCC28
SCC2692AC1A44-T 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44
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