- 您现在的位置：买卖IC网 > PDF目录98079 > SCANPSC100FDMQB (NATIONAL SEMICONDUCTOR CORP) SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28 PDF资料下载
参数资料
| 型号： | SCANPSC100FDMQB |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28 |
| 封装： | CERAMIC, DIP-28 |
| 文件页数： | 5/27页 |
| 文件大小： | 381K |
| 代理商： | SCANPSC100FDMQB |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页
Serial Scan Interface (SSI) (Continued)
The TMS Shifter/Buffer block diagram is shown in
These two blocks take parallel data and serialize it for shift
operations through the serial port pins TMS0 and TMS1.
Double-buffering is achieved by configuring the shifter/buffer
asa2x8 FIFO. Write and shift operations are controlled by
a local state machine that accepts stimulus from the PPI,
Mode Registers, CNT32 and TCK Control section. The TMS
outputs always change on the falling edge of SCK. The order
of shifting is least significant bit first. TMS(1:0) are forced
high upon RST low. TMS(1:0) are TRI-STATEd when OE is
high.
Write operations are completed if the shifter/buffer is not full
(independent of whether shifter/buffer is enabled or dis-
abled). Otherwise they are ignored. Shifting occurs when the
following conditions are all true:
TMS is enabled with its respective mode bit.
TMS shifter/buffer is not empty.
TCK is enabled according to the logic in TCK Control.
When shift operations are not enabled, the TMS output
retains its last state. During long shift sequences, the TMS
shifter/buffer can be disabled and held static so that shift
operations are concentrated only on TDI and TDO. The TMS
output also retains its last state when Test Loop-Back opera-
tions are in progress.
Local select circuitry is used to toggle back and forth be-
tween the two registers of the “FIFO” when shifting. At any
given time, one register is selected for shift operations. The
other holds its previous state or can accept new parallel
data. Shift register selection changes due to the following
two events:
CNT3 in TCK Control signals that 8 bits have been
shifted. This event is used for basic toggling between
each of the two shift registers.
CNT32 enabled and at terminal count. This event is used
to account for scan lengths which are not multiples of
eight. When shift register selection changes due to this
signal, any data remaining in the shift register is unused.
AUTO TMS HIGH MODE . This feature is included in the
TMS shifter/buffer block to improve the efficiency of the
PSC100 in supporting shift operations within the 1149.1
devices connected to the SSI. Shifting data and instructions
into 1149.1 compliant devices requires that their TAP con-
trollers be sequenced to the Shift-DR or Shift-IR states (see
Figure 8). Once in this state, shifting occurs by holding TMS
low and clocking TCK. The last bit is shifted when the TAP
controller transitions to the EXIT1 state. This transition re-
quires a logic 1 on TMS. The Auto TMS High feature, en-
abled by setting bit 1 of Mode Register 0, automatically
creates a logic 1 on the TMS lines of the PSC100 when
CNT32 = 1. Consequently, the last bit is shifted out without
having to load specific TMS data into the shifter/buffer.
Note: Auto TMS High mode creates a logic 1 on both TMS lines (i.e., TMS0
and TMS1). Therefore, when using the Auto TMS High feature, all
1149.1 devices connected to the TMS line not participating in the
current JTAG test operations should be placed in the Test-Logic-Reset
TAP controller state to prevent inadvertent TAP controller transitions.
TDO SHIFTER/BUFFER
The TDO Shifter/Buffer block diagram is shown in
This block takes parallel data and serializes it for shift op-
erations through the serial port pin TDO. During normal shift
modes, double-buffering is achieved by configuring the
shifter/buffer asa2x8 FIFO. This block can also be config-
ured as a 32-bit Pseudo Random Pattern Generator (PRPG)
with two additional 8-bit parallel-to-serial shift registers. Write
and shift operations are controlled by a local state machine
that accepts stimulus from the PPI, Mode Registers, CNT32,
and the TCK Control section. The TDO output always
changes on the falling edge of SCK. The order of shifting is
least significant bit first. TDO is forced high upon RST low.
TDO is TRI-STATEd when OE is high.
Write operations are completed if the shifter/buffer is not full
(independent of whether shifter/buffer is enabled or dis-
abled). Otherwise they are ignored.
Shifting occurs when the following conditions are all true:
TDO is enabled with its respective mode bit.
TDO shifter/buffer is not empty.
TCK is enabled according to the logic in TCK Control.
When shift operations are not enabled, the TDO output
retains its last state. The TDO output also retains its last
state when Test Loop-Back operations are in progress.
Local select circuitry is used to toggle back and forth be-
tween the two registers of the “FIFO” when shifting. At any
given time, one register is selected for shift operations. The
other holds its previous state or can accept new parallel
data. Shift register selection changes due to the following
two events:
CNT3 in TCK Control signals that 8 bits have been
shifted. This event is used for basic toggling between
each of the two shift registers.
CNT32 enabled and at terminal count. This event is used
to account for scan lengths which are not multiples of
eight. When shift register selection changes due to this
signal, any data remaining in the shift register is unused.
PRPG MODE . By setting MODE1(4), the TDO Shifter/Buffer
is reconfigured as a 32-bit PRPG (Pseudo Random Pattern
Generator) using the primitive polynomial:
F(X) = X
32 +X22 +X2 +X+1
The PSC100 was developed to support both 1149.1 and
non-1149.1 serial test methodologies. Since 1149.1 compli-
ant devices include boundary scan registers on control pins
(i.e. OE), which must remain fixed during boundary scan
interconnect testing, generating pseudo-random patterns
with PRPG mode provides limited usefulness for boundary
scan test operations. PRPG mode may provide usefulness
in other serial test or non-test related implementations which
do not require fixed bits in the serial chain.
Figure 12 shows a block diagram of the Linear Feedback
Shift Register hookup.
SCANPSC100F
Embedded
www.national.com
13
相关PDF资料 |
PDF描述 |
|---|---|
| SCANPSC100FLMQB | SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28 |
| SCB68172C2F28 | VME BUS CONTROLLER, CDIP28 |
| SCC2691AC1D24 | 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PDSO24 |
| SCC2691AE1A28 | 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PQCC28 |
| SCC2692AC1A44-T | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SCANPSC100FLMQB | 制造商:Texas Instruments 功能描述: |
| SCANPSC100FSC | 功能描述:接口 - 专用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
| SCANPSC100FSCX | 功能描述:接口 - 专用 Emb Boun Scan Cont RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
| SCANPSC110 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110_ZFC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
发布紧急采购，3分钟左右您将得到回复。