参数资料
型号: SCANPSC100FDMQB
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: 微控制器/微处理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, CDIP28
封装: CERAMIC, DIP-28
文件页数: 25/27页
文件大小: 381K
代理商: SCANPSC100FDMQB
TIMING WAVEFORMS
Note 1: Valid data is provided on the RDY line a tpd1 after R/W is asserted
low or a tpd2after valid data is decoded on A2:0. The RDY line will remain high
until the addressed register is ready to participate in the write operation. This
condition only applies when writing to a shifter/buffer and is eliminated (i.e.,
RDY will go low immediately once valid) when using shifter/buffer status
polling (discussed later in this datasheet).
Note 2: Valid data will not appear on D7:0 (and RDY will remain high) until
the addressed register is ready to participate in the read operation. When the
addressed register becomes ready (i.e., a byte is available to be read), valid
data will be placed on the D7:0 bus and the RDY pin will go low allowing the
bus cycle to continue. This read cycle delay only applies when reading the
TDI shifter/buffer and is eliminated when using shifter/buffer status poling.
10032503
FIGURE 2. Write Cycle
10032504
FIGURE 3. Read Cycle
SCANPSC100F
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相关PDF资料
PDF描述
SCANPSC100FLMQB SPECIALTY MICROPROCESSOR CIRCUIT, CQCC28
SCB68172C2F28 VME BUS CONTROLLER, CDIP28
SCC2691AC1D24 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PDSO24
SCC2691AE1A28 1 CHANNEL(S), 38.4K bps, SERIAL COMM CONTROLLER, PQCC28
SCC2692AC1A44-T 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44
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