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参数资料
| 型号： | SDED7-256M-N9Y |
| 厂商： | SANDISK CORP |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA115 |
| 封装： | 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115 |
| 文件页数： | 51/87页 |
| 文件大小： | 1675K |
| 代理商： | SDED7-256M-N9Y |
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Rev. 1.2
Design Considerations
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
55
92-DS-1205-10
9.6
Connecting Control Signals
9.6.1
Demux Interface
When using a demux NOR-like interface, connect the control signals as follows:
A[16:0] – Connect these signals to the host address signals (see Section 9.10 for
platform-related considerations). The A0 signal may be connected to either the host
CPU A0 signal or to VSS.
D[15:0] – Connect these signals to the host data signals (see Section 9.10 for
platform-related considerations).
OE# (Output Enable) and Write Enable (WE#) – Connect these signals to the host
RD# and WR# signals, respectively.
CE# (Chip Enable) – Connect this signal to the memory address decoder. Most
RISC/mobile processors include a programmable decoder to generate various Chip
Select (CS) outputs for different memory zones. These CS signals can be
programmed to support different wait states to accommodate mDOC H3 timing
specifications.
RSTIN# (Power-On Reset In) – Connect this signal to the host active-low Power-On
Reset signal.
ID0 (Chip Identification) – This signal must be connected to VSS if the host uses
only one mDOC H3. If more than one device is being used, refer to Section 9.9 for
more information on device cascading.
BUSY# (Busy) – This signal indicates when the device is ready for first access after
reset. It may be connected to an input port of the host, or alternatively it may be used
to hold the host in a wait-state condition. The later option is required for hosts that
boot from mDOC H3.
DMARQ# (DMA Request) – Output used to control multi-page DMA operations.
Connect this output to the DMA controller of the host platform.
IRQ# (Interrupt Request) – Connect this signal to the host interrupt.
Lock# (LOCK) – Connect to a logical 0 to prevent the usage of the protection key to
open a protected partition. Connect to logical 1 in order to enable usage of protection
keys.
CLK (Clock) – This input is used to support Burst operation when reading flash data.
Refer to Section 9.8 for further information on Burst operation.
9.6.2
Multiplexed Interface
mDOC H3 can use a multiplexed interface to connect to a multiplexed bus. In this configuration,
mDOC H3 AVD# signal is driven by the host's AVD# signal, and the D[15:0] balls, used for
both address inputs and data, are connected to the host AD[15:0] bus.
This mode is automatically entered when a falling edge is detected on AVD#. This edge must
occur after RSTIN# is negated and before OE# and CE# are both asserted; i.e., the first read
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SDED7-512M-NAT | 功能描述:IC MDOC H3 512MB FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| SDED7-512M-NAY | 功能描述:IC MDOC H3 512MB FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| SDEG-15P | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
| SDEG-15P05 | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
| SDEG-15S | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
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