参数资料
型号: SDED7-256M-N9Y
厂商: SANDISK CORP
元件分类: 存储控制器/管理单元
英文描述: FLASH MEMORY DRIVE CONTROLLER, PBGA115
封装: 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115
文件页数: 55/87页
文件大小: 1675K
代理商: SDED7-256M-N9Y
Rev. 1.2
Design Considerations
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
59
92-DS-1205-10
Valid address
D0
D1
D2
D3
D4
D5
D6
D7
Burst CLK
CE
OE
AVD
Data
Latency=1
Figure 17: Multiplexed Read Busrt Mode
Notes: 1. Note: AVD must be asserted on the following clock after the assertion of CE.
2. No collision should be allowed between the AVD and OE signal.
9.8.2.2
Write Mode
The Write mode is similar to the Read mode with the following exceptions:
WAIT_STATE = 0: 1 clock added.
WAIT_STATE = 1: 2 clocks added.
WAIT_STATE = 2: 3 clocks added.
WAIT_STATE = 3: 4 clocks added.
Figure 1818: Demux Write Burst Mode
Note: WE is sampled on the 1st clock after CE assertion. It must be active (low) for at least one
clock cycle, after that the status of the WE signal is not important ().
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