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参数资料
| 型号： | SDED7-256M-N9Y |
| 厂商： | SANDISK CORP |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA115 |
| 封装： | 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115 |
| 文件页数： | 58/87页 |
| 文件大小： | 1675K |
| 代理商： | SDED7-256M-N9Y |
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Rev. 1.2
Design Considerations
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
61
92-DS-1205-10
9.10 Platform-Specific Issues
This section discusses hardware design issues for major embedded RISC processor families.
9.10.1 Wait State
Wait states can be implemented only when mDOC H3 is designed in a bus that supports a Wait
state insertion, and supplies a WAIT signal.
9.10.2 Big and Little Endian Systems
mDOC H3 is a Little Endian device. Therefore, byte lane 0 (D[7:0]) is its Least Significant Byte
(LSB) and byte lane 1 (D[15:8]) is its Most Significant Byte (MSB). Within the byte lanes, bit
D0 and bit D8 are the least significant bits of their respective byte lanes. mDOC H3 can be
connected to a Big Endian device in one of two ways:
1. Make sure to identify byte lane 0 and byte lane 1 of your processor. Then, connect the data
bus so that the byte lanes of the CPU match the byte lanes of mDOC H3. Pay special
attention to processors that also change the bit ordering within the bytes (for example,
PowerPC). Failing to follow these rules results in improper connection of mDOC H3, and
prevents the DOC Driver from identifying it.
2. If needed, set the SWAP bits in the Endian Control register. This enables byte swapping
when used with big endian 16-bit hosts.
9.10.3 Busy Signal
The Busy signal (BUSY#) indicates that mDOC H3 has not yet completed internal initialization.
After reset, BUSY# is asserted while the IPL is downloaded into the internal boot block. Once
the download process is completed, BUSY# is de-asserted. It can be used to delay the first access
to mDOC H3 until it is ready to accept valid cycles.
Note: mDOC H3 does NOT use this signal to indicate that the flash is in busy state (e.g.
program, read, or erase).
9.10.4 Working with 16/32-Bit Systems
mDOC H3 uses a 16-bit data bus and supports 16-bit data access by default. However, it can be
configured to support 32-bit data access mode. This section describes the connections required
for each mode.
The default of the DOC Driver for mDOC H3 is set to work in 16-bit mode. It must be specially
configured to support 32-bit mode. Please see DOC Driver or TrueFFS 7.1 documentation for
further details.
Note: The mDOC H3 data bus must be connected to the Least Significant Bits (LSB) of the
system.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SDED7-512M-NAT | 功能描述:IC MDOC H3 512MB FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| SDED7-512M-NAY | 功能描述:IC MDOC H3 512MB FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| SDEG-15P | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
| SDEG-15P05 | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
| SDEG-15S | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
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