- 您现在的位置：买卖IC网 > PDF目录85252 > SDED7-256M-N9Y (SANDISK CORP) FLASH MEMORY DRIVE CONTROLLER, PBGA115 PDF资料下载
参数资料
| 型号： | SDED7-256M-N9Y |
| 厂商： | SANDISK CORP |
| 元件分类： | 存储控制器/管理单元 |
| 英文描述： | FLASH MEMORY DRIVE CONTROLLER, PBGA115 |
| 封装： | 12 X 9 MM, 1.20 MM HEIGHT, FBGA-115 |
| 文件页数： | 53/87页 |
| 文件大小： | 1675K |
| 代理商： | SDED7-256M-N9Y |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页
Rev. 1.2
Design Considerations
mDOC H3 EFD Featuring Embedded TrueFFS Data Sheet
57
92-DS-1205-10
2. Level DMARQ# output is asserted while the data is available for read, or data can be
accepted for write. The EDGE bit is set to 0 for this mode.
The following steps are required in order to initiate a DMA operation:
1. If the DMA controller supports an edge-sensitive DMARQ# signal, then initialize the DMA
controller to transfer 512 bytes (or your chosen data block size) upon each DMA request. If
the DMA controller supports a level-sensitive DMARQ# signal, then initialize the DMA
controller to transfer data continuously while DMARQ# is asserted.
2. Set in the DMA Control register values of EDGE bit, PULSE_WIDTH and DMA polarity
corresponding to settings of the host DMA controller. This can be done only once after
system power-up.
3. Enable DMA transfer with DMA_EN bit in the DMA control register.
4. If host DMA controller detects the de-assertion of the DMARQ# signal too late (and
attempts to transfer additional words as a result), then DMARQ# can be configured to be de-
asserted earlier by using the DMA Negation Register.
5. Program host DMA controller to transfer the same number of sectors as will be given in
following logical command.
6. Issue the DMA data-transfer read/write command with same number of sectors to transfer as
given in the previous step (prior to this, the device should be instructed to perform transfers
in DMA-mode).
Upon command completion IRQ# will be asserted (it is recommended to use IRQ# when
working with DMA). In case of a failure, less than expected amount of data could be transferred.
In commands that use DMA transfer, IRQ# is activated only at the completion of the whole
command; while in commands that do not use DMA transfer IRQ# is typically activated with
every data transfer.
Default setting of DMARQ# is level and active-low. It can be modified using the flHwConfig
DOC Driver API. For more information see the DOC Driver 1.0 Block Device (BD) Software
Developer Kit (SDK) Developer Guide..
9.8.2
Synchronous Burst Operation
In this mode the host reads full sections of 16-bit words synchronized to the CLK input.
Burst operation is controlled by 5 bit fields in each Burst Mode Control register (one for Burst
read and one for Burst write): BURST_EN, WAIT_STATE, LATENCY, HOLD and LENGTH.
For full details on this register, please refer to Section 7.
Burst Read / Write mode is enabled by setting the BURST_EN bit in each Burst Mode Control
register.
相关PDF资料 |
PDF描述 |
|---|---|
| SPMC68336AVFT20 | 32-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP160 |
| SPMC68336GCFT20 | 32-BIT, MROM, 20.97 MHz, MICROCONTROLLER, PQFP160 |
| SC104002VPVR2 | 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP112 |
| S9S12XF512J0MLH | MICROCONTROLLER, QFP64 |
| SC9S12XF512J0CLMR | MICROCONTROLLER, QFP112 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SDED7-512M-NAT | 功能描述:IC MDOC H3 512MB FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| SDED7-512M-NAY | 功能描述:IC MDOC H3 512MB FBGA RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| SDEG-15P | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
| SDEG-15P05 | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
| SDEG-15S | 制造商:HRS 制造商全称:HRS 功能描述:STRAIGHT/METAL PCB D-SUB |
发布紧急采购，3分钟左右您将得到回复。