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参数资料
| 型号： | SI5110-H-GL |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 19/36页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 99LFBGA |
| 标准包装： | 168 |
| 系列： | SiPHY™ |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | SONET/SDH |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 99-LBGA |
| 供应商设备封装： | 99-BGA（11x11） |
| 包装： | 托盘 |
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Si5110
26
Rev. 1.5
G8
LPTM
I
LVTTL
Loop Timed Operation.
When this input is set low, the recovered clock from
the receiver is divided down and used as the refer-
ence source for the transmit CMU. The narrowband
setting for the DSPLL CMU is sufficient to provide
SONET compliant jitter generation and jitter transfer
on the transmit data and clock outputs (TXD-
OUT,TXCLKOUT). Set this pin high for normal opera-
tion.
Note: This input has an internal pullup.
C4
LTR
I
LVTTL
Lock-to-Reference.
When the LTR input is set low, the receiver PLL will
lock to the selected reference clock. This function can
be used to force a stable output clock on the RXCLK1
and RXCLK2 outputs when no valid input data signal
is applied to RXDIN.
When the LTR input is set high, the receiver PLL will
lock to the RXDIN signal (normal operation).
Note: This input has an internal pullup.
A2
PHASEADJ
I
Sampling Phase Adjust.
Applying an analog voltage to this pin allows adjust-
ment of the sampling phase across the data eye.
Tieing this input to VREF nominally centers the sam-
pling phase.
E10
F10
REFCLK+,
REFCLK–
I
LVPECL
Differential Reference Clock.
This input is used as the Si5110 reference clock when
the REFSEL input is set high (REFSEL = 1). The ref-
erence clock sets the operating frequency of the
Si5110 transmit CMU, which is used to generate the
high-speed transmit clock TXCLKOUT. The reference
clock is also used by the Si5110 receiver CDR to cen-
ter the PLL during lock acquisition, and as a reference
for determination of the receiver lock status.
The REFCLK frequency is either 1/16th or 1/32nd of
the serial data rate (nominally 155 or 78 MHz,
respectively). The REFCLK frequency is selected
using the REFRATE input.
When REFSEL = 1, a valid reference clock must be
present.
Pin
Number(s)
Name
I/O
Signal Level
Description
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相关代理商/技术参数 |
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|---|---|
| SI5110-H-XL4 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI5110-H-ZL3 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI511BBA200M000BAGR | 制造商:Silicon Laboratories Inc 功能描述:SLLSI511BBA200M000BAGR OSC (200MHZ) |
| SI51210 | 制造商:SILABS 制造商全称:SILABS 功能描述:TWO OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR |
| Si51210-A01AFM | 功能描述:时钟发生器及支持产品 6 TDFN microClockgen SL Clock RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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