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参数资料
| 型号： | SI5110-H-GL |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 20/36页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 99LFBGA |
| 标准包装： | 168 |
| 系列： | SiPHY™ |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | SONET/SDH |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 99-LBGA |
| 供应商设备封装： | 99-BGA（11x11） |
| 包装： | 托盘 |
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Si5110
Rev. 1.5
27
F3
REFRATE
I
LVTTL
Reference Clock Rate Select.
The REFRATE input sets the frequency for the
REFCLK input. When REFRATE is set high, the
REFCLK frequency is 1/16th the serial data rate
(nominally 155 MHz). When REFRATE is set low, the
REFCLK frequency is 1/32nd the serial data rate
(nominally 78 MHz).
The REFRATE input has no effect when the REFSEL
input is set low.
Note: This input has an internal pullup.
J7
REFSEL
I
LVTTL
Reference Clock Selection.
This input selects the reference clock source to be
used by the Si5110 transmitter and receiver. The ref-
erence clock sets the operating frequency of the
Si5110 transmit CMU, which is used to generate the
high-speed transmit clock TXCLKOUT. The reference
clock is also used by the Si5110 receiver CDR to cen-
ter the PLL during lock acquisition, and as a reference
for determination of the receiver lock status.
When REFSEL = 0, the low-speed data input clock,
TXCLK4IN, is used as the reference clock. When
REFSEL = 1, the reference clock provided on
REFCLK is used.
Note: This input has an internal pullup.
E3
RESET
I
LVTTL
Device Reset.
Forcing this input low for at least 1
s causes a device
reset. For normal operation, this pin should be held
high.
Note: This input has an internal pullup.
A6, B6, C5,
G3, J3–4,
K2
RSVD_GND
Reserved Tie To Ground.
Must be connected directly to GND for proper
operation.
B5
RXAMPMON
O
Analog
Receiver Amplitude Monitor.
The RXAMPMON output provides an analog output
signal
that
is
proportional
to
the
input
signal
amplitude.
See
for
the
relationship
between RXAMPON and RXDIN. This signal is active
when SLICEMODE is asserted.
B8
B7
RXCLK1+,
RXCLK1–
OLVDS
Differential Receiver Clock Output 1.
The clock recovered from the signal present on
RXDIN is divided down to the parallel output word rate
and output on RXCLK1. In the absence of data, a sta-
ble clock on RXCLK1 can be maintained by asserting
LTR.
Pin
Number(s)
Name
I/O
Signal Level
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5110-H-XL4 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI5110-H-ZL3 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI511BBA200M000BAGR | 制造商:Silicon Laboratories Inc 功能描述:SLLSI511BBA200M000BAGR OSC (200MHZ) |
| SI51210 | 制造商:SILABS 制造商全称:SILABS 功能描述:TWO OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR |
| Si51210-A01AFM | 功能描述:时钟发生器及支持产品 6 TDFN microClockgen SL Clock RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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