- 您现在的位置：买卖IC网 > PDF目录9967 > SI5110-H-GL (Silicon Laboratories Inc)IC TXRX SONET/SDH LP HS 99LFBGA PDF资料下载
参数资料
| 型号： | SI5110-H-GL |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 22/36页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 99LFBGA |
| 标准包装： | 168 |
| 系列： | SiPHY™ |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | SONET/SDH |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 99-LBGA |
| 供应商设备封装： | 99-BGA（11x11） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
Si5110
Rev. 1.5
29
D8
RXMSBSEL
I
LVTTL
Receive Data Bus Bit Order Select.
This input determines the order of the received data
bits on the RXDOUT[3:0] output bus.
For RXMSBSEL = 0, the first data bit received is out-
put on RXDOUT0 and following data bits are output
on RDOUT1 through RXDOUT3.
For RXMSBSEL = 1, the first data bit is output on
RXDOUT3 and following data bits are output on
RXDOUT2 through RXDOUT0.
Note: This input has an internal pulldown.
A4
RXREXT
Receiver External Bias Resistor.
This resistor is used by the receiver circuitry to estab-
lish bias currents within the device. This pin must be
connected to GND through a 3.09 k
1resistor.
A5
RXSQLCH
I
LVTTL
Receiver Data Squelch.
When this input is low, the data on RXDOUT[3:0] is
forced to a zero state. Set RXSQLCH high for normal
operation.
The RXSQLCH input is ignored when operating in
Diagnostic Loopback mode (DLBK = 0).
Note: This input has an internal pullup.
A3
SLICELVL
I
Slicing Level Adjustment.
Applying an analog voltage to this pin allows adjust-
ment of the slicing level applied to the input data eye.
Tying this input to VREF sets the slicing offset to 0.
C6
SLICEMODE
I
LVTTL
Slice Level Adjustment Mode.
The SLICEMODE input is used to select the mode of
operation for slicing level adjustment. When SLICE-
MODE = 0, Absolute Slice mode is selected. When
SLICEMODE = 1, Proportional Slice mode is selected.
Note: This input has an internal pulldown.
K8
K7
TXCLK4IN+,
TXCLK4IN–
ILVDS
Differential Transmit Data Clock Input.
The rising edge of this input clocks data present on
TXDIN into the device. TXCLK 4IN is also used as the
Si5100 reference clock when the REFSEL input is set
low.
K6
K5
TXCLK4OUT+,
TXCLK4OUT–
OLVDS
Divided Down Transmit Clock Output.
This clock output is generated by dividing down the
high-speed output clock, TXCLKOUT, by a factor of 4.
It is intended for use in counter clocking schemes that
transfer data between the system framer and the
Si5110. (See REFSEL and REFRATE descriptions.)
Pin
Number(s)
Name
I/O
Signal Level
Description
相关PDF资料 |
PDF描述 |
|---|---|
| MAX11206EEE+T | IC ADC 20BIT 16QSOP |
| GTC06A-20-18P | CONN PLUG 9POS STRAIGHT W/PINS |
| IDT723634L15PF8 | IC FIFO SYNC 512X36X2 128QFP |
| MAX11626EEE+T | IC ADC 12BIT 4CH 16QSOP |
| IDT72815LB25BG8 | IC FIFO SYNC DUAL 512X18 121BGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5110-H-XL4 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI5110-H-ZL3 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI511BBA200M000BAGR | 制造商:Silicon Laboratories Inc 功能描述:SLLSI511BBA200M000BAGR OSC (200MHZ) |
| SI51210 | 制造商:SILABS 制造商全称:SILABS 功能描述:TWO OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR |
| Si51210-A01AFM | 功能描述:时钟发生器及支持产品 6 TDFN microClockgen SL Clock RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
发布紧急采购，3分钟左右您将得到回复。