参数资料
型号: SI5320-H-BL
厂商: Silicon Laboratories Inc
文件页数: 14/34页
文件大小: 0K
描述: IC CLOCK MULT SONET/SDH 63-PBGA
标准包装: 260
系列: DSPLL®
类型: 时钟乘法器
PLL:
输入: LVTTL
输出: CML
电路数: 1
比率 - 输入:输出: 1:1
差分 - 输入:输出: 是/是
频率 - 最大: 693MHz
除法器/乘法器: 是/是
电源电压: 3.135 V ~ 3.465 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 63-LBGA
供应商设备封装: 63-PBGA(9x9)
包装: 托盘
Si5320
Rev. 2.5
21
2.13. Design and Layout Guidelines
Precision clock circuits are susceptible to board noise
and EMI. To take precautions against unacceptable
levels of board noise and EMI affecting performance of
the Si5320, consider the following:
Power the device from 3.3 V since the internal
regulator provides at least 40 dB of isolation to the
VDD25 pins (which power the PLL circuitry).
Use an isolated local plane to connect the VDD25
pins. Avoid running signal traces over or below this
plane without a ground plane in between.
Route all I/O traces between ground planes as much
as possible
Maintain an input clock amplitude in the 200 mVPP to
500 mVPP differential range.
Excessive high-frequency harmonics of the input
clock should be minimized. The use of filters on the
input clock signal can be used to remove high-
frequency harmonics.
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