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| 型号： | SI5320-H-BL |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 17/34页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK MULT SONET/SDH 63-PBGA |
| 标准包装： | 260 |
| 系列： | DSPLL® |
| 类型： | 时钟乘法器 |
| PLL： | 是 |
| 输入： | LVTTL |
| 输出： | CML |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:1 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 693MHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 63-LBGA |
| 供应商设备封装： | 63-PBGA（9x9） |
| 包装： | 托盘 |
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Si5320
24
Rev. 2.5
Table 11. Si5320 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
B4
FXDDELAY
I*
LVTTL
Fixed Delay Mode.
Set high to disable hitless recovery from digital hold
mode. This configuration is useful in applications
that require a known, or constant, input-to-output
phase relationship.
When this pin is high, hitless switching from digital
hold mode back to a valid clock input is disabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY high, the clock output
changes as necessary to re-establish the initial/
default input-to-output phase relationship that is
established after powerup or reset. The rate of
change is determined by the setting of BWSEL[1:0].
When this pin is low, hitless switching from digital
hold mode back to a valid clock input is enabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY low, the device enables
"phase build out" to absorb the phase difference
between the clock output and the clock input so that
the phase change at the clock output is minimized.
In this case, the input-to-output phase relationship
following the transition out of digital hold mode is
determined by the phase relationship at the time
that switching occurs.
Note:
FXDDELAY should remain at a static high or static
low level during normal operation. Transitions on
this pin are allowed only when the RSTN/CAL pin
is low. FXDDELAY must be set high when DBLBW
is set high.
D1
E1
CLKIN+
CLKIN–
I
AC Coupled
200–500 mVPPD
(See Table 2)
System Clock Input.
Clock input to the DSPLL circuitry. The frequency of
the CLKIN signal is multiplied by the DSPLL to gen-
erate the CLKOUT clock output. The input-to-output
frequency multiplication factor is set by selecting the
clock input range and the clock output range. The
frequency of the CLKIN clock input can be in the 19,
38, 77, 155, 311, or 622 MHz range (nominally
19.44, 38.88, 77.76, 155.52, 311.04, or
622.08 MHz) as indicated in Table 3 on page 7. The
clock input frequency is selected using the INFRQ-
SEL[2:0] pins. The clock output frequency is
selected using the FRQSEL[1:0] pins. An additional
scaling factor of either 255/238 or 238/255 may be
selected for FEC operation using the FEC[1:0] con-
trol pins.
*Note:
The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
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| Si5320-H-GL | 功能描述:时钟发生器及支持产品 SONET/SDH Precisn Clock Multiplr RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SI5320-X-BC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:SONET/SDH PRECISION CLOCK MULTIPLIER IC |
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| SI5321-EVB | 功能描述:时钟和定时器开发工具 G.709FEC & 66/64Sc 19-2.5GHz Output RoHS:否 制造商:Texas Instruments 产品:Evaluation Modules 类型:Clock Conditioners 工具用于评估:LMK04100B 频率:122.8 MHz 工作电源电压:3.3 V |
| SI5321-F-BC | 功能描述:时钟合成器/抖动清除器 FOR NEW DESIGNS RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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