- 您现在的位置：买卖IC网 > PDF目录16791 > SI5338-EVB (Silicon Laboratories Inc)BOARD EVALUATION SI5338 PDF资料下载
参数资料
| 型号： | SI5338-EVB |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 20/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION SI5338 |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | Si5338 |
| 主要属性： | LVPECL/LVDS：160 kHz 至 700 MHz，<1 ps RMS 标准抖动，零 ppm 频率错误 |
| 次要属性： | 基于 USB 的 GUI，用于编程，I2C/SMBus 兼容接口，1.8、2.5 或 3.3 V |
| 已供物品： | 板，线缆，CD，样品 |
| 产品目录页面： | 628 (CN2011-ZH PDF) |
| 相关产品： | 336-1555-5-ND - IC CLK GEN QUAD 200MHZ 24-QFN 336-1554-5-ND - IC CLK GEN QUAD 350MHZ 24-QFN 336-1553-5-ND - IC CLK GEN QUAD 700MHZ 24-QFN |
| 其它名称： | 336-1556 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页当前第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
Si5338
Rev. 1.3
27
3.10.4. Output Synchronization
Upon power up or a soft_reset the Si5338 synchronizes
the output clocks. With normal output polarity (no output
clock inversion), the Si5338 synchronizes the output
clocks to the falling, not rising edge. Synchronization at
the rising edge can be done by inverting all the clocks
that are to be synchronized.
3.10.5. Output R Divider
When the requested output frequency of a channel is
below 5 MHz, the Rn (n = 0,1,2,3) divider needs to be
set and enabled. This is automatically done in register
maps generated by the ClockBuilder Desktop. When
the Rn divider is active the step size range of the
frequency
increment
and decrement
function
will
decrease by the Rn divide ratio. The Rn divider can be
set to {1, 2, 4, 8, 16, 32}.
Non-unity settings of R0 will affect the Finc/Fdec step
size at the MultiSynth0 output. For example, if the
MultiSynth0 output step size is 2.56 MHz and R0 = 8,
the step size at the output of R0 will be 2.56 MHz
divided by 8 = .32 MHz. When the Rn divider is set to
non-unity, the initial phase offset of the CLKn output with
respect to other CLKn outputs is not guaranteed.
3.10.6. Zero-Delay Mode
The Si5338 supports an optional zero delay mode of
operation for applications that require minimal input-to-
output delay. In this mode, one of the device output
clocks is fed back to the feedback input pin (IN4 or IN5/
IN6) to implement an external feedback path which
nullifies the delay between the reference input and the
output clocks. Figure 15 shows the Si5338 in a typical
zero-delay configuration. It is generally recommended
that Clk3 be LVDS and that the feedback input be pins 5
and 6. For the differential input configuration to pins 5
and 6, see Figure 3 on page 18. The zero-delay mode
combined with the phase increment/decrement feature
allows unprecedented flexibility in generating clocks
with precise edge alignment.
Figure 15. Si5338 in Zero Delay Clock
Generator Mode
3.10.7. Spread Spectrum
To help reduce electromagnetic interference (EMI), the
Si5338 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread
energy across a broader range of frequencies, lowering
system EMI. The Si5338 implements spread spectrum
using its patented MultiSynth technology to achieve
previously unattainable precision in both modulation
rate and spreading magnitude as shown in Figure 16.
Through I2C control, the Spread spectrum can be
applied to any output clock, any clock frequency, and
any spread amount from ±0.1% to ±2.5% center spread
and –0.1% to –5% down spread.
The spreading rate is limited to 30 to 63 kHz.
The Spread Spectrum is generated digitally in the output
MultiSynths which means that the Spread Spectrum
parameters
are
virtually
independent
of
process,
voltage and temperature variations. Since the Spread
Spectrum is created in the output MultiSynths, through
I2C each output channel can have independent Spread
Spectrum parameters. Without the use of I2C (NVM
download only) the only supported Spread Spectrum
parameters are for PCI Express compliance composing
100 MHz clock, 31.5 kHz spreading frequency with the
choice of the spreading.
Rev A devices provide native support for both down and
center spread. Center spread is supported in rev B
devices by up-shifting the nominal frequency and using
down-spread register parameters. Consult the Si5338
Reference Manual for details.
Note: If you currently use center spread on a revision A and
would like to migrate to a revision B device, you must
generate a new register map using either ClockBuilder
Desktop or the equations in the Si5338 Reference
Manual. Center spread configurations for Revisions A
and B are not compatible.
Clk0
MS2
MS3
R2
R3
P2
Si5338
PLL
R0
R1
MS1
MS0
P1
Clk
Input
Clk1
Clk2
Clk3
相关PDF资料 |
PDF描述 |
|---|---|
| H3AAH-2606G | IDC CABLE - HSC26H/AE26G/HSC26H |
| 0982660138 | CBL 12POS 0.5MM JMPR TYPE D 1' |
| 0982661084 | CBL 37POS 0.5MM JMPR TYPE D 6" |
| HMC08DRTH | CONN EDGECARD 16POS DIP .100 SLD |
| EBC43DCSD-S288 | CONN EDGECARD 86POS .100 EXTEND |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SI5338F-A01839-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338F-A01839-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| Si5338F-A-GM | 功能描述:时钟发生器及支持产品 I2C-PRGRMBL clock generatr 0.16-200MHz RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| SI5338F-A-GMR | 功能描述:时钟发生器及支持产品 I2C-Program Clk Gen 0.16-200MHz Pin-Ctrl RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| Si5338F-B-GM | 功能描述:时钟发生器及支持产品 I2C-PRGRMBL clock generatr 0.16-200MHz RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
发布紧急采购，3分钟左右您将得到回复。