参数资料
| 型号： | SM3E-19.44M |
| 厂商： | Connor-Winfield |
| 文件页数： | 19/36页 |
| 文件大小： | 0K |
| 描述： | IC MOD TIMING 19.440MHZ STRAT 3E |
| 标准包装： | 1 |
| 系列： | SM3 |
| 类型： | 定时模块，系统时钟 |
| PLL： | 是 |
| 主要目的： | 以太网，ADM，DSLAM，SONET/SDH，Stratum，TDM |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 8:3 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 19.44MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 32-DIP 模块 |
| 包装： | 管件 |
| 其它名称： | CW643 SM3E 19.44M SM3E19.44M |
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SM3E Data Sheet #:
TM054
Page 26 of 36 Rev: 04 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Application Notes continued
Master/Slave Configuration–Apairofdevicesareinterconnectedbycross-couplingtheirrespectiveM/S Outputs or
Output1totheotherdevice’sM/S REFinput(SeeFigure8).Additionally,thereferenceinputsforeachdevicewouldtypicallybe
correspondinglythesame,sothatwhenaMaster/Slaveswitchoccurs,synchronizationwouldcontinuewiththesamereference.The
referencesmaybedrivenbythesamesignaldirectlyorviaseparatedrivers,astheredundancyofthatpartofthesystemrequires.
Distributionpathlengthsarenotcriticalhere,asaphasebuild-outwilloccurwhenadeviceswitchesfromslavetomaster.
ThepathlengthsofthetwoM/SOutputto
M/S REFsignalsisofinterest,however.Theyneednotbethesame.However,to
accommodatepathlengthdelays,theSM3Eprovidesaprogrammablephaseskewfeature,whichallowstheapplicationtooffsetthe
outputclockfromthecross-referencesignalby-32nsto+31.75ns.Thisoffsetmaythereforebeprogrammedtoexactlycompensate
fortheactualpathlengthdelayassociatedwiththeparticularapplication’scross-referencetraces.Theoffsetmaybefurtheradjusted
toaccommodateanyoutputclockdistributionpathdelaydifferences.PhaseoffsetisprogrammedbywritingtothePhase_Offset
register,andistypicallyaone-timedeviceinitializationfunction.(SeeregisterdescriptionandRegisterAccessControlsections).Thus,
master/slaveswitcheswiththeSM3Edevicesmaybeaccomplishedwithnear-zerophasehits.
ForapplicationsthatuseHardwareControlonly(i.e.phaseoffsetprogrammingisnotavailable),itisdesirabletokeepthecross
couplepathlengthsataminimumandrelativelyequalinlength,asthepathlengthwillappearasaphasehitintheslaveclockoutput
whenamaster/slaveswitchoccursinaHardwareControlconfiguration.
Master/Slave Operation and Control–TheMaster/Slavestateisalwaysmanuallycontrolledbytheapplication.Masterorslave
stateofadeviceisdeterminedbythe
MASTER SELECT pin.Choosingthemaster/slavestatesisafunctionoftheapplication,based
ontheconfigurationoftherestofthesystemandpotentialdetectedfaultconditions.
Master/slaveswitchesshouldbeperformedwithminimaldelaybetweenswitchingthestatesofeachofthetwodevices.Thiscan
beeasilyaccomplished,forexample,bycontrollingthemaster/slavestatewithasinglesignal,coupledtooneofthedevicesthrough
aninverter.WhileperformingMaster/Slaveswitches,onehastomakesurethatbothmodulesarenotinslavemode.Thiscreatesa
“TimingLoop”thatcancauseundesirableeffects.
InthecaseofRegisterAccessAutomaticControlmode,wherereferenceselectionisautomatic,itisnecessarytoreadthe
operationalmodeBITS3-0)fromthemaster’s
Op_Moderegisterandwriteittotheslave’sOp_Moderegister.Themaster’sreference
selectionwillthenbeusedbytheslavewhenitbecomesmaster.Inadditiontohavingthereferencespopulatedthesame,andinthe
sameorderforbothdevices,itisdesireabletowritethereferencefrequencyandpriorityregisters
Ref(1-8)_Frq_Priorityandthe
Ref_Maskregisterstothesamevaluesforbothdevicestoensureseamlessmaster/slaveswitches.
Reset–Deviceresetisaninitializationtimefunction,whichresetsinternallogicandregistervalues.Aresetisperformed
automaticallywhenthedeviceispoweredup.Registersreturntotheirdefaultvalues,asnotedintheregisterdescriptions.Device
modeandfunctionalityfollowingaresetaredeterminedbythestateofthevarioushardwarecontrolpins.
Holdover History Accumulation and Maintenance -- Holdoverhistoryaccumulationandmaintenancemaybecontrolledin
greaterdetailifregisterbusaccesstothedeviceisprovided.Holdoverhistoryaccumulationandcontrolencompassesthreedevice
internalregisters,threebusaccessregistersforcontrolandaccess,andtwostatusbitsintheDPLL_Statusregister.
Oncelockhasbeenachieved,holdoverhistoryiscompiledintheaccumulationregister.ItistransferredtotheActiveholdoverhistory
whenitisready(typicallyinabout15minutes).The“HoldoverAvailable”bitandoutputpinaresetto“1”.Fromthenon,theActive
holdoverhistoryiscontinuallyupdatedandkeptinsyncwiththeholdoverhistoryaccumulationregister.(SeeFigure11).
Hold Over History
Accumulation Register
Active
Hold Over History
Backup
Hold Over History
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