参数资料
型号: SM3E-19.44M
厂商: Connor-Winfield
文件页数: 24/36页
文件大小: 0K
描述: IC MOD TIMING 19.440MHZ STRAT 3E
标准包装: 1
系列: SM3
类型: 定时模块,系统时钟
PLL:
主要目的: 以太网,ADM,DSLAM,SONET/SDH,Stratum,TDM
输入: LVCMOS
输出: LVCMOS
电路数: 1
比率 - 输入:输出: 8:3
差分 - 输入:输出: 无/无
频率 - 最大: 19.44MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 32-DIP 模块
包装: 管件
其它名称: CW643
SM3E 19.44M
SM3E19.44M
SM3E Data Sheet #:
TM054
Page 30 of 36 Rev: 04 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
SM3E Application Note on Interrupts
TheSM3/3Emodulesupportseightdifferentinterruptsandappearsin
INTR_EVENT (0x12)register.Eachinterruptcanbe
individuallyenabledordisabledviathe
INTR_ENABLE (0x13)register.Eachbitenablesordisablesthecorrespondinginterruptfrom
assertingtheSPI_INTpin.Interrupteventsstillappearinthe
INTR_EVENT (0x12)registerindependentoftheirenablestate.All
interruptsareclearedonce
INTR_EVENT (0x12)registerisread.Theinterruptsare
1. Anyreferencechangingfromavailabletonotavailable
2. Anyreferencechangingfromnotavailabletoavailable
3. M/SREFchangingfromactivitytonoactivity
4. M/SREFchangingfromnoactivitytoactivity
5. DPLLModestatuschange
6. Activereferencechange
7. LossofSignal
8. LossofLock
Interrupts and Reference change in Autonomous mode:Interruptscanbeusedtodeterminethecauseofareferencechange
inautonomousmode.LetusassumethatthemoduleiscurrentlylockedtoREF1.ThemoduleswitchestoREF2andSPI_INTpinis
asserted.Theuserreadsthe
INTR_EVENT (0x12)register.
Ifthemoduleisoperatinginautonomousnon-revertivemode,thecausecanbedeterminedfrombits4,5,6and7.Bit5issetto
indicateActivereferencechange.IfBit6issetthenthecauseofthereferencechangeisLossofActiveReference.IfBit7issetthen
thecauseofthereferencechangeisaLossofLockalarmontheactivereference.
Ifthemoduleisoperatinginautonomousrevertivemode,thecausecanbedeterminedfrombits1,4,5,6and7.Bit5issetto
indicateActivereferencechange.IfBit6issetthenthecauseofthereferencechangeisLossofActiveReference.IfBit7issetthen
thecauseofthereferencechangeisaLossofLockalarmontheactivereference.IfBit1issetthenthecauseofthereference
changeistheavailabilityofahigherpriorityreference.
Note:TheDPLLModeStatusChangebit(Bit4)isalsosettoindicateachangein
DPLL_STATUS (0x11)register,duringaninterrupt
causedbyareferencechange.Thedatain
DPLL_STATUS (0x11)registerhoweverisnotusefulindeterminingthecauseofa
referencechange.Thisisbecausebits0-2ofthisregisteralwaysreflectsthestatusofthecurrentactivereferenceandhencecannot
beusedtodeterminethestatusofthelastactivereference.
Interrupts in Manual Mode:Inmanualoperatingmode,whentheactivereferencefailsduetoaLossofSignalorLossofLockalarm,
aninterruptisgenerated.Forexample,incaseofaLossofSignal,bits4and6of
INTR_EVENT (0x12)registerwouldbesetto
indicateLossofSignalandDPLLModeStatusChange.Theusermaychoosetoreadthe
DPLL_STATUS (0x11)register,thoughin
manualmodebit6of
INTR_EVENT (0x12)registerisamirrorofbit0ofDPLL_STATUS (0x11)register.ThisholdstrueforaLossof
Lockalarm,wherebit7of
INTR_EVENT (0x12)registerisamirrorofbit1ofDPLL_STATUS (0x11)register.
Application Notes continued
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