参数资料
| 型号： | SM3E-19.44M |
| 厂商： | Connor-Winfield |
| 文件页数： | 8/36页 |
| 文件大小： | 0K |
| 描述： | IC MOD TIMING 19.440MHZ STRAT 3E |
| 标准包装： | 1 |
| 系列： | SM3 |
| 类型： | 定时模块，系统时钟 |
| PLL： | 是 |
| 主要目的： | 以太网，ADM，DSLAM，SONET/SDH，Stratum，TDM |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 8:3 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 19.44MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 32-DIP 模块 |
| 包装： | 管件 |
| 其它名称： | CW643 SM3E 19.44M SM3E19.44M |
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SM3E Data Sheet #:
TM054
Page 16 of 36 Rev: 04 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Register Descriptions and Operation continued
Intr_Event, 0x12 (R)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Lossof
Activerefer-
DPLLMode M/SRef
M/SRef
Anyrefer-
Lock
Signal
encechange
status
Changefrom Changefrom
erencechange erencechange
change
noactivityto
activitytono
fromnot
fromavailable
activity
availableto
abletonot
available
Interrupt state = 1. When an enabled interrupt occurs, the SPI_INT pin is asserted, active low. All interrupts are cleared
and the SPI_INT pin pulled high when the register is read. Reset default is 0. See Detailed Description section under
Interrupts and Reference Change in Autonomous Mode and Interrupts in Manual Mode
Intr_Enable, 0x13 (R/W)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EnableInter- EnableInter- EnableInter-
EnableInter- EnableInter-
EnableInter-
ruptevent7: ruptevent6: ruptevent5:
ruptevent4: ruptevent3:
ruptevent2:
ruptevent1:
ruptevent0:
1:Enable
0:Disable
Default:0
Enables or disables the corresponding interrupts from asserting the SPI_INT pin. Interrupt events still appear in the
Intr_Event register independent of their “enable” state. Reset default is interrupts disabled.
Ref(1-8)_Frq_Offset, 0x14 ~ 0x1b (R)
Bit7~Bit0
2’scomplementvalueoffrequencyoffsetbetweenreferenceandcalibratedlocaloscillator,0.2ppmresolution
These registers indicate the frequency offset, in 0.2ppm resolution, between each reference and the local calibrated
oscillator.
0x14 - 0x1b correspond to Ref1 - Ref8.
Ref(1-8)_Frq_Priority, 0x1c ~ 0x23 (R/W)
Bit7~Bit4
Bit3
Bit2~Bit0
Frequency
Revertivity
Priority
0000:None
1:revertive
0:highest
0001:8kHz
0:non-revertive
7:lowest
0010:1.544MHz
Default:0,
Default:0
0011:2.048MHz
nonrevertive
0100:12.96MHz
0101:19.44MHz
0110:25.92MHz
0111:38.88MHz
1000:51.84MHz
1001:77.76MHz
1010-1111:Reserved
BITS 2 - 0 indicate the priority of each reference for use in automatic reference selection mode (bit 1 of the Ctl_Mode
register =0). In manual reference selection mode (bit 1 of the Ctl_Mode register = 1), these BITS are read-only and will
contain either the reset default or values written when last in automatic reference selection mode. For equal priority
values, lower reference numbers have higher priority.
Bit 3 specifies if the reference is revertive or non-revertive in automatic reference selection mode. When a reference
fails, the next highest priority “available” (signal present, non-masked, and acceptable frequency offset) reference will
be selected. When a reference returns, it will be switched to only if it is of higher priority and the current active reference
is marked “Revertive”.
BITS 7 - 4 indicate the auto-detected frequency for each reference. Invalid frequencies may result in erroneous device
operation. If there is no activity on a reference, bits 7-4will be = 0000. Bits 7-4 are read only. 0x1c - 0x23 correspond
to Ref1 - Ref8.
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