参数资料
| 型号： | SM3E-19.44M |
| 厂商： | Connor-Winfield |
| 文件页数： | 3/36页 |
| 文件大小： | 0K |
| 描述： | IC MOD TIMING 19.440MHZ STRAT 3E |
| 标准包装： | 1 |
| 系列： | SM3 |
| 类型： | 定时模块，系统时钟 |
| PLL： | 是 |
| 主要目的： | 以太网，ADM，DSLAM，SONET/SDH，Stratum，TDM |
| 输入： | LVCMOS |
| 输出： | LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 8:3 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 19.44MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 32-DIP 模块 |
| 包装： | 管件 |
| 其它名称： | CW643 SM3E 19.44M SM3E19.44M |
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SM3E Data Sheet #:
TM054
Page 11 of 36 Rev: 04 Date: 01/26/11
Copyright 2011 The Connor-Winfield Corp. All Rights Reserved
Specifications subject to change without notice
Detailed Description continued
Output Signals and Frequency
Output 1istheprimarychipoutput,andinlockedmodeissynchronizedtotheselectedreference.Output 1maybeanyofthe
followingfrequencies:12.96MHz,19.44MHz,25.92MHz,38.88MHz,51.84MHzor77.76MHz.
M/S_Out isan8kHzoutputavailableasaframereferenceorsynchronizationsignalforcross-coupledpairsofSM3Edevices
operatedinmaster/slavemode.Inmastermode,M/S_Outissynchronizedtotheselectedreference.Inslavemode,M/S_Outisin
phasewiththe
M/S REF offsetbythevaluewrittentothePhase_offset register(+31.75to-32nS,with.25nSresolution).M/S_Out
maybea50%dutycyclesignal,orvariablehigh-goingpulsewidth,asdeterminedbythe
Ctl_ModeandFr_Pulse_Widthregisters.
Invariablepulsewidthmode,thewidthmaybefrom1to15multiplesofthe
Output 1cycletime.SeeRegisterDescriptionsand
Operationsection.
BITS_ClkistheBITSclockoutputateither1.544MHzor2.048MHz.ItisselectedbytheT1/E1inputanditsstatemaybereadinbit
3oftheCtl_Moderegister.WhenT1/E1=1,theBITSfrequencyis1.544MHz,andwhenT1/E1=0,theBITSfrequencyis2.048MHz.
Interrupts
TheSM3Emodulesupportseightdifferentinterruptsandappearsin
INTR_EVENT (0x12)register.Eachinterruptcanbe
individuallyenabledordisabledviathe
INTR_ENABLE (0x13)register.Eachbitenablesordisablesthecorrespondinginterruptfrom
assertingthe
SPI_INTpin.InterrupteventsstillappearintheINTR_EVENT (0x12)registerindependentoftheirenablestate.All
interruptsareclearedonce
INTR_EVENT (0x12)registerisread.Theinterruptsare:
Anyreferencechangingfromavailabletonotavailable
Anyreferencechangingfromnotavailabletoavailable
M/S REFchangingfromactivitytonoactivity
M/S REFchangingfromnoactivitytoactivity
DPLLModestatuschange
Referenceswitchinautomaticreferenceselectionmode
LossofSignal
LossofLock
Interrupts and Reference Change in Autonomous Mode
Interruptscanbeusedtodeterminethecauseofareferencechangeinautonomousmode.Letusassumethatthemoduleis
currentlylockedto
REF1.ThemoduleswitchestoREF2andSPI_INTpinisasserted.TheuserreadstheINTR_EVENT (0x12)
register.
Ifthemoduleisoperatinginautonomousnon-revertivemode,thecausecanbedeterminedfrombits4,5,6and7.Bit5issetto
indicateActivereferencechange.IfBit6issetthenthecauseofthereferencechangeisLossofActiveReference.IfBit7issetthen
thecauseofthereferencechangeisaLossofLockalarmontheactivereference.
Ifthemoduleisoperatinginautonomousrevertivemode,thecausecanbedeterminedfrombits1,4,5,6and7.Bit5issetto
indicateActivereferencechange.IfBit6issetthenthecauseofthereferencechangeisLossofActiveReference.IfBit7isset
thenthecauseofthereferencechangeisaLossofLockalarmontheactivereference.IfBit1issetthenthecauseofthereference
changeistheavailabilityofahigherpriorityreference.
Note:TheDPLLModeStatusChangebit(Bit4)isalsosettoindicateachangeinDPLL_STATUS (0x11)register,duringan
interruptcausedbyareferencechange.Thedatain
DPLL_STATUS (0x11)registerhoweverisnotusefulindeterminingthecauseof
areferencechange.Thisisbecausebits0-2ofthisregisteralwaysreflectsthestatusofthecurrentactivereferenceandhencecannot
beusedtodeterminethestatusofthelastactivereference.
Interrupts in Manual Mode
Inmanualoperatingmode,whentheactivereferencefailsduetoaLossofSignalorLossofLockalarm,aninterruptisgenerated.
Forexample,incaseofaLossofSignal,bits4and6of
INTR_EVENT (0x12) registerwouldbesettoindicateLossofSignaland
DPLLModeStatusChange.Theusermaychoosetoreadthe
DPLL_STATUS (0x11)register,thoughinmanualmodebit6ofINTR_
EVENT (0x12)registerisamirrorofbit0ofDPLL_STATUS (0x11)register.ThisholdstrueforaLossofLockalarm,wherebit7of
INTR_EVENT (0x12) registerisamirrorofbit1ofDPLL_STATUS (0x11)register.
Internal Clock Calibration
Theinternalclockmaybecalibratedbywritingafrequencyoffsetv.s.nominalfrequencyintotheCalibrationregister.This
calibrationisusedbythesynchronizationsoftwaretocreateafrequencycorrectedfromtheactualinternalclockoutputbythevalue
writtentotheCalibrationregister.Seeregisterdescriptions.
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