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参数资料
型号： SN65LVDS302_07
厂商： Texas Instruments, Inc.
英文描述： PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
中文描述： 可编程27位串行到并行接收机
文件页数： 13/41页
文件大小： 1412K
代理商： SN65LVDS302_07
www.ti.com
RECOMMENDED OPERATING CONDITIONS
(1)
SN65LVDS302
SLLS733B–JUNE 2006–REVISED FEBRUARY 2007
MIN
TYP
MAX
UNIT
V
DD
V
DDPLLA
V
DDPLLD
V
DDLVDS
Supply voltages
1.65
1.8
1.95
V
Test set-up see
Figure 7
f
CLK
≤
50MHz; f(noise) = 1Hz to 2 GHz
f
CLK
> 50MHz; f(noise) = 1Hz to 1MHz
f
CLK
> 50 MHz; f(noise) > 1MHz
100
100
40
85
Supply voltage noise magnitude
50MHz (all supplies)
V
DDn(PP)
mV
T
A
CLK+ and CLK–
Operating free-air temperature
–40
°
C
1-Channel receive mode, see
Figure 3
2-Channel receive mode, see
Figure 4
3-Channel receive mode, see
Figure 5
Standby mode
(2)
, See
Figure 16
4
8
15
30
65
MHz
f
CLK
±
Input Pixel clock frequency
20
500
65
kHz
%
t
DUTCLK
D0+, D0–, D1+, D1–, D2+, D2-, CLK+, and CLK–
|V
ID
|
Magnitude of differential input
voltage
V
ICM
Input Voltage Common Mode Range
CLK Input Duty Cycle
35
|V
D0+
-V
D0-
|, |V
-V
|, |V
-V
|,
|V
CLK+
-V
CLK-
| during normal operation
Receive or Acquire mode
Stand-by mode
V
– V
with n=D0, D1, D2, or CLK
and m=D0, D1, D2, or CLK
70
200
mV
0.6
1.2
V
0.9
×
V
DDLVDS
–100
V
ICM
Input Voltage Common Mode
Variation between all SubLVDS
inputs
Differential Input Voltage Amplitude
Variation between all SubLVDS
inputs
Input Rise and Fall Time
Input Rise or Fall Time mismatch
between all SubLVDS inputs
LS0, LS1, CPOL, SWAP, RXEN, F/S
V
ICMOSH
High-level input voltage
V
ICMOSL
Low-level input voltage
t
inRXEN
RXEN input pulse duration
R[7:0], G[7:0], B[7:0], VS, HS, PCLK, CPE
C
L
Output load capacitance
100
mV
V
ID
V
– V
with n=D0, D1, D2, or CLK
and m=D0, D1, D2, or CLK
–10
10
%
t
R/F
t
R/F
RXEN at VDD; see figure 6-2
t
– t
and t
– t
with n=D0, D1,
D2, or CLK and m=D0, D1, D2, or CLK
800
100
ps
–100
ps
0.7
×
V
DD
V
DD
V
V
μ
s
0
0.3
×
V
DD
10
10
pF
(1)
(2)
Unused single-ended inputs must be held high or low to prevent them from floating.
PCLK input frequencies lower than 500 kHz force the SN65LVDS302 into standby mode. Input frequencies between 500 kHz and 3
MHz may or may not activate the SN65LVDS302. Input frequencies beyond 3 MHz activate the SN65LVDS302. Input frequencies
between 500 kHz and 4 MHz are not recommended, and can cause PLL malfunction.
13
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