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| 型号： | SN65LVDS302_07 |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER |
| 中文描述： | 可编程27位串行到并行接收机 |
| 文件页数： | 7/41页 |
| 文件大小： | 1412K |
| 代理商： | SN65LVDS302_07 |
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FUNCTIONAL DESCRIPTION
Deserialization Modes
The SN65LVDS302 receiver has three modes of operation controlled by link-select pins LS0 and LS1.
Table 2
shows the deserializer modes of operation.
1-Channel Mode
D0 +/- CHANNEL
CLK +
B7 B6
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0
B5 B4 B3 B2 B1 B0 VS HS DE resres CP R7 R6
CP
res
res
CLK -
2-Channel Mode
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 VS res CP
res
B7 B6
G3 G2 G1 G0
B5 B4 B3 B2 B1 B0 HS DE res
CP
R7 R6
G3 G2
CLK +
CLK -
D0 +/- CHANNEL
D1 +/- CHANNEL
SN65LVDS302
SLLS733B–JUNE 2006–REVISED FEBRUARY 2007
Table 2. Logic Table: Link Select Operating Modes
LS1
0
LS0
0
Mode of Operation
Data Links Status
1ChM
1-channel mode (30-bit serialization rate)
D0 active;
D1, D2 disabled
D0, D1 active;
D2 disabled
D0, D1, D2 active
Reserved
0
1
2ChM
2-channel mode (15-bit serialization rate)
1
1
0
1
3ChM
3-channel mode (10-bit serialization rate)
Reserved
While LS0 and LS1 are held low, the SN65LVDS302 receives payload data over a single SubLVDS data pair,
D0. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 30. The internal
high speed clock is used to shift in the data payload on D0 and to deserialize 30 bits of data.
Figure 3
illustrates
the timing and the mapping of the data payload into the 30-bit frame. The internal high speed clock is divided by
a factor of 30 to recreate the pixel clock and the data payload with the pixel clock is presented on the output
bus. The reserved bits and parity bit are not output. While in this mode, the PLL can lock to a clock that is in the
range of 4 MHz through 15 MHz. This mode is intended for smaller video display formats that do not need the
full bandwidth capabilities of the SN65LVDS302.
Figure 3. Data and Clock Input in 1-ChM (LS0 and LS1 = low)
While LS0 is held high and LS1 is held low, the SN65LVDS302 receives payload data over two SubLVDS data
pairs, D0 and D1. The PLL locks to the SubLVDS clock input and internally multiplies the clock by a factor of 15.
The internal high speed clock is used to shift in the data payload on D0 and D1 and to deserialize 15 bits of data
from each pair.
Figure 4
illustrates the timing and the mapping of the data payload into the 30-bit frame. The
internal high speed clock is divided by a factor of 15 to recreate the pixel clock, and the data payload with pixel
clock is presented on the output bus. The reserved bits and parity bit are not output. While in this mode the PLL
can lock to a clock that is in the range of 8 MHz through 30 MHz.
Figure 4. Data and Clock Input in 2-ChM (LS0 = high; LS1 = low)
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| SN65LVDS302ZQE | 功能描述:串行器/解串器 - Serdes Program 27B Display Ser Interface RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| SN65LVDS302ZQER | 功能描述:串行器/解串器 - Serdes Programmable 27B Displ Ser Interface RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| SN65LVDS303ZQE | 功能描述:IC PROG 27BIT SERDES TX 80-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 串行器，解串行器 系列:65LVDS 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 功能:解串器 数据速率:2.5Gbps 输入类型:串行 输出类型:并联 输入数:- 输出数:24 电源电压:1.8 V ~ 3.3 V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:64-TQFP 裸露焊盘 供应商设备封装:64-TQFP-EP（10x10） 包装:管件 |
| SN65LVDS303ZQER | 功能描述:串行器/解串器 - Serdes QVGA-VGA 27B Display Serial Interface RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
| SN65LVDS304ZQER | 功能描述:串行器/解串器 - Serdes QVGAVGA 27B Display Ser Interface RoHS:否 制造商:Texas Instruments 类型:Deserializer 数据速率:1.485 Gbit/s 输入类型:ECL/LVDS 输出类型:LVCMOS 输入端数量:1 输出端数量:20 工作电源电压:2.375 V to 2.625 V 工作温度范围:0 C to + 70 C 封装 / 箱体:TQFP-64 |
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