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| 型号： | SN65LVDS302_07 |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER |
| 中文描述： | 可编程27位串行到并行接收机 |
| 文件页数： | 17/41页 |
| 文件大小： | 1412K |
| 代理商： | SN65LVDS302_07 |
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4 MHz
9 %
8 MHz
9 %
20 MHz
8.7 %
15 MHz
8.1 %
30 MHz
8.1 %
Spec Limit
1 ChM
Spec Limit
2 ChM
Spec Limit
3 ChM
65 MHz
7.5 %
9.0
8.5
7.5
7.0
6.5
8.0
6.0
0
10
20
30
40
50
60
70
PCLK - Frequency - MHz
P
12
11
10
9
8
7
6
5
4
P
PLL - Frequency - MHz
100
0
200
300
400
600
500
700
TIMING CHARACTERISTICS
ps
480
f
30
2
1
CLK
-
·
·
ps
480
f
15
2
1
CLK
-
·
·
ps
410
f
10
2
1
CLK
-
·
·
SN65LVDS302
SLLS733B–JUNE 2006–REVISED FEBRUARY 2007
Figure 6. SN65LVDS302 PLL Bandwidth (also showing the SN65LVDS301 PLL bandwidth)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
1ChM: x=0..29, f
PCLK
=15 MHz;
RXEN at V
DD
, V
IH
,
V
=GND, R
L
=100
, test setup
as in
Figure 8
, test pattern as in
Table 11
f
CLK
=15 MHz
(4)
f
CLK
=4 MHz to 15 MHz
(5)
630
2ChM: x = 0..14,
f
=30 MHz
RXEN at V
DD
, V
IH
=V
,
V
=GND, R
L
=100
, test setup
as in
Figure 8
, test pattern as in
Table 12
f
CLK
=30 MHz
(4)
f
CLK
=8 MHz to 30 MHz
(5)
630
Receiver input skew
margin; see
(3)
and
Figure 43
t
(RSKMx
ps
3ChM:
RXEN at V
, V
=V
,
V
=GND, test setup as in
Figure 8
, test pattern as in
Table 13
f
CLK
= 65 MHz
(4)
f
= 20 MHz to 65
MHz
(5)
360
(1)
Receiver Input Skew Margin (t
) is the timing margin available for transmitter output pulse position (t
), interconnect skew, and
interconnect inter-symbol interference. tRSKM represents the reminder of the serial bit time not taken up by the receiver strobe
uncertainty;. The t
assumes a bit error rate better than 10
-12
.
t
is indirectly proportional to the internal set-up and hold time uncertainty, ISI and duty cycle distortion from the front end receiver,
the skew missmatch between CLK and data D0, D1, and D2, as well as the PLL cycle-to-cycle jitter.
This includes the receiver internal set-up and hold time uncertainty, all PLL related high-frequency random and deterministic jitter
components that impact the jitter budget, ISI and duty cycle distortion from the front end receiver, and the skew between CLK and data
D0, D1, and D2; The pulse position min/max variation is given with a bit error rate target of 10
–12
; Measurements of the total jitter are
taken over a sample amount of > 10
–12
samples.
The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temp ranges.
These Minimum and Maximum Limits are simulated only.
(2)
(3)
(4)
(5)
17
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