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| 型号： | SN65LVDS302_07 |
| 厂商： | Texas Instruments, Inc. |
| 英文描述： | PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER |
| 中文描述： | 可编程27位串行到并行接收机 |
| 文件页数： | 36/41页 |
| 文件大小： | 1412K |
| 代理商： | SN65LVDS302_07 |
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How To Determine Interconnect Skew and Jitter Budget
Designing a reliable data link requires examining the interconnect skew and jitter budget. The sum of all
transmitter, PCB, connector, FPC, and receiver uncertainties must be smaller than the available serial bit time.
The highest pixel clock frequency defines the available serial bit time. The transmitter timing uncertainty is
defined by t
PPOS
in the transmitter data sheet. For a bit-error-rate target of
≤
10-12, the measurement duration
for tPPOS is
1012. The SN65LVDS302 receiver can tolerate a maximum timing uncertainty defined by t
RSKM
.
The interconnect budget is calculated by:
PPOS
RSKM
erconnect
int
t
t
t
-
=
(1)
Example:
ps
639
t
t
t
PPOS
RSKM
erconnect
int
=
-
=
(2)
RSKM
D0, D1, D2
RX internal sampling clock
Data Period /2
Ideal receiver strobe position
Ideal TPPosndata transition
R
SPosn
: Receiver input strobe position (min and max)
R
SPosn
(max) - R
SPosn
(min) = Skew
RX
+ S&H
RX
+ TJ
(RXPLL(non-trackable)
SkewRX Receiver input skew (skew between CLK and Dx input)
S&HRX Receiver input latch Sample & Hold uncertainty
TJ(RXPLL(non-trackable): Intrinsic RX PLL jitter above RX PLL bandwidth; PLL
TJ>
f(BWRX); TJ=RJ[ps-rms]*14 + DJ[ps]
Tppos: Transmitter output pulse position (min and max)
T
PPosx
(max) -T
PPosx
(min) = TJ
TXPLL(non-trackable)
+ t
TXskew
+ t
TXDJ
TJTXPLL(non-trackable): non-trackable TX PLL jitter; this jitter is the integration
TJ=RJ[ps-rms]*14 + DJ[ps]
tTXskewtransmitter output skew (skew between CLK and data)
tTXIDJTransmitter Deterministic JItter of TX output stage (includes TX
Intersymbol Interference ISI)
T
PPosn
(max)
T
PPosn
(min)
RSKM: Receiver Skew Margin
RSKM = SKEW
PCB
+ XTALK
PCB
+ ISI
PCB
SKEW
PCB: PCB induced Skew (trace + connector);
XTALK
PCB: PCB induced cross-talk;
ISIPCB Inter-symbol interference of PCB; is
dependent on interconnect frequency loss; may be
zero for short interconnects.
RSPosn(max)
RSPosn(min)
RSKM
SN65LVDS302
SLLS733B–JUNE 2006–REVISED FEBRUARY 2007
f
PCLK
(max) = 23 MHz (VGA display resolution, 60 Hz)
Transmission mode: 2-ChM; t
PPOS
(SN65LVDS301) = 330 ps
Target bit error rate: 10
-12
t
RSKM
(SN65LVDS302) = 1/(2*15*f
PCLK
) – 480 ps = 969 ps
The interconnect budget for cable skew & ISI needs to be smaller than:
Figure 43. Jitter Budget
36
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