参数资料
型号: SN65LVDS302_07
厂商: Texas Instruments, Inc.
英文描述: PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
中文描述: 可编程27位串行到并行接收机
文件页数: 33/41页
文件大小: 1412K
代理商: SN65LVDS302_07
www.ti.com
APPLICATION INFORMATION
Preventing Increased Leakage Currents in Control Inputs
A floating (left open) CMOS input allows leakage currents to flow from V
DD
to GND. Do not leave any CMOS
input unconnected or floating. Every input must be connected to a valid logic level V
IH
or V
OL
while power is
supplied to V
DD
. This also minimizes the power consumption of standby and power down mode.
Power Supply Design Recommendation
For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all
ground terminals directly to this plane.
SN65LVDS302 DECOUPLING RECOMMENDATION
The SN65LVDS302 was designed to operate reliably in a constricted environment with other digital switching
ICs. In cell phone designs, the SN65LVDS302 often shares a power supply with various other ICs. The
SN65LVDS302 can operate with power supply noise as specified in Recommend Device Operating Conditions.
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS302 power pins. The
use of four ceramic capacitors (two 0.01
μ
F and two 0.1
μ
F) provides good performance. At the very least, it is
recommended to install one 0.1
μ
F and one 0.01
μ
F capacitor near the SN65LVDS302. To avoid large current
loops and trace inductance, the trace length between decoupling capacitor and IC power inputs pins must be
minimized. Placing the capacitor underneath the SN65LVDS302 on the bottom of the PCB is often a good
choice.
VGA APPLICATION
Figure 40
shows a possible implementation of a standard 640x480 VGA display. The LVDS301 interfaces to the
SN65LVDS302, which is the corresponding receiver device to deserialize the data and drive the display driver.
The pixel clock rate of 22 MHz assumes ~10% blanking overhead and 60 Hz display refresh rate. The
application assumes 24-bit color resolution. Also shown is how the application processor provides a powerdown
(reset) signal for both serializer and the display driver. The signal count over the Flexible Printed Circuit board
(FPC) could be further decreased by using the standby option on the SN65LVDS302 and pulling RXEN high
with a 30 k
resistor to V
DD
.
S
R
22MHz
27
PCLK
R[7:0]
G[7:0]
B[7:0]
HS,VS,DE
D[7:0]
D[15:8]
D[23:16]
HS,VS,DE
Pixel CLK
V
G
2x0.01uF
2x0.1uF
L
L
T
1.8V
V
G
2x0.01uF
2x0.1uF
L
L
R
1.8V
D0+
D0-
CLK+
CLK-
D1+
D1-
D0+
D0-
CLK+
CLK-
D1+
D1-
GND
1.8V
2.7V
GND
1.8V
2.7 V
GND
GND
L
r
22MHz
27
PCLK
R[7:0]
G[7:0]
B[7:0]
HS,VS,DE
S
Serial port interface
(3-wire IF
)
3
Application
Processor
(e.g. OMAP)
SN65LVDS301
SN65LVDS302
Video Mode Display
Driver
FPC
22MHz
330Mbps
330Mbps
E
If FPC wire count is critical
connection with a pull
,
replace this
up resistor at RXEN
-
SN65LVDS302
SLLS733B–JUNE 2006–REVISED FEBRUARY 2007
Figure 40. Typical VGA Display Application
33
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