参数资料
| 型号： | SOUNDBITE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 14/68页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO AUDIO DEVELOPMENT |
| 标准包装： | 1 |
| 系列： | Symphony™ soundBite |
| 主要目的： | 音频，音频处理 |
| 已用 IC / 零件： | DSPB56371 |
| 主要属性： | 最高 8 通道数字音频 |
| 次要属性： | USB、I2C、SPI 接口 |
| 已供物品： | 板，缆线，CD |
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Signal/Connection Descriptions
3.3
Ground
Table 3. Grounds
Ground Name
PLLA_GND(1)
PLLP_GND(1)
Description
PLL Ground —The PLL ground should be provided with an extremely low-impedance path to
ground. The user must provide adequate external decoupling capacitors.
PLLD_GND(1) PLL Ground —The PLL ground should be provided with an extremely low-impedance path to
ground. The user must provide adequate external decoupling capacitors.
CORE_GND (4) Core Ground —The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user must
provide adequate external decoupling capacitors.
IO_GND (5)
SHI, ESAI, ESAI_1, DAX and Timer I/O Ground —IO_GND is an isolated ground for the SHI, ESAI,
ESAI_1, DAX and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
3.4
SCAN
Table 4. SCAN Signals
Signal
Name
SCAN
Type
Input
State
During
Reset
Input
Signal Description
SCAN —Manufacturing test pin. This pin should be pulled low.
Internal Pull down resistor.
3.5
Clock and PLL
Table 5. Clock and PLL Signals
Signal
Name
EXTAL
Type
Input
State
during
Reset
Input
Signal Description
External Clock Input —An external clock source must be connected to EXTAL in
order to supply the clock to the internal clock generator and PLL.
This input is 5 V tolerant .
PINIT/NMI
Input
Input
PLL Initial/Nonmaskable Interrupt —During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion
and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is
a negative-edge-triggered nonmaskable interrupt (NMI) request internally
synchronized to internal system clock.
Internal Pull up resistor.
This input is 5 V tolerant.
DSP56371 Data Sheet, Rev. 4.1
14
Freescale Semiconductor
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| SOURCE INSPECTION | 制造商:Vishay Dale 功能描述:FACTORY INSPECTION |
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