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MPC5634M Microcontroller Data Sheet, Rev. 6
Overview
Freescale Semiconductor
16
— Pad configuration control for virtual I/O via DSPI serialization
System reset monitoring and generation
— Power-on reset support
— Reset status register provides last reset source to software
— Glitch detection on reset input
— Software controlled reset assertion
External interrupt
— 11 interrupt requests
— Rising or falling edge event detection
— Programmable digital filter for glitch rejection
— Critical Interrupt request
— Non-Maskable Interrupt request
GPIO
— GPIO function on 80 I/O pins
— Virtual GPIO on 64 I/O pins via DSPI serialization (requires external deserialization device)
— Dedicated input and output registers for setting each GPIO and Virtual GPIO pin
Internal multiplexing
— Allows serial and parallel chaining of DSPIs
— Allows flexible selection of eQADC trigger inputs
— Allows selection of interrupt requests between external pins and DSPI
1.3.8
ECSM
The error correction status module provides status information regarding platform memory errors reported by error-correcting
codes.
1.3.9
Flash
Devices in the MPC5634M family provide up to 1.5 MB of programmable, non-volatile, flash memory. The non-volatile
memory (NVM) can be used for instruction and/or data storage. The flash module includes a Fetch Accelerator, that optimizes
the performance of the flash array to match the CPU architecture and provides single cycle random access to the flash @
80 MHz. The flash module interfaces the system bus to a dedicated flash memory array controller. For CPU ‘loads’, DMA
transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface
to flash memory. The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which prefetches sequential
lines of data from the flash array into the buffer. Prefetch buffer hits allow no-wait responses. Normal flash array accesses are
registered and are forwarded to the system bus on the following cycle, incurring three wait-states. Prefetch operations may be
automatically controlled, and are restricted to instruction fetch.
The flash memory provides the following features:
Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword
reads are supported. Only aligned word and doubleword writes are supported.
Fetch Accelerator
— Architected to optimize the performance of the flash with the CPU to provide single cycle random access to the
flash up to 80 MHz system clock speed
— Configurable read buffering and line prefetch support
— Four line read buffers (128 bits wide) and a prefetch controller
Hardware and software configurable read and write access protections on a per-master basis