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| 型号： | SPC5632MF0MLQA4 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | FLASH, 40 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 0.50 MM PITCH, 1.40 HEIGHT, ROHS COMPLIANT, LQFP-144 |
| 文件页数： | 40/122页 |
| 文件大小： | 1173K |
| 代理商： | SPC5632MF0MLQA4 |
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MPC5634M Microcontroller Data Sheet, Rev. 6
Overview
Freescale Semiconductor
24
be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable
operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. FlexCAN module ‘A’ contains 64
message buffers (MB); FlexCAN module ‘C’ contains 32 message buffers.
The FlexCAN module provides the following features:
Based on and including all existing features of the Freescale TouCAN module
Full Implementation of the CAN protocol specification, Version 2.0B
— Standard data and remote frames
— Extended data and remote frames
— Zero to eight bytes data length
— Programmable bit rate up to 1 Mbit/s
Content-related addressing
64 / 32 message buffers of zero to eight bytes data length
Individual Rx Mask Register per message buffer
Each message buffer configurable as Rx or Tx, all supporting standard and extended messages
Includes 1088 / 544 bytes of embedded memory for message buffer storage
Includes a 256-byte and a 128-byte memories for storing individual Rx mask registers
Full featured Rx FIFO with storage capacity for six frames and internal pointer handling
Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended, 16 standard or 32 partial (8 bits)
IDs, with individual masking capability
Selectable backwards compatibility with previous FlexCAN versions
Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock
Listen only mode capability
Programmable loop-back mode supporting self-test operation
3 programmable Mask Registers
Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority
Time Stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Warning interrupts when the Rx and Tx Error Counters reach 96
Independent of the transmission medium (an external transceiver is assumed)
Multi master concept
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Low power mode, with programmable wake-up on bus activity
1.3.18
System timers
The system timers provide two distinct types of system timer:
Periodic interrupts/triggers using the Peripheral Interrupt Timer (PIT)
Operating system task monitors using the System Timer Module (STM)
1.3.18.1
Peripheral Interrupt Timer (PIT)
The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has
no external input or output pins and is intended to be used to provide system ‘tick’ signals to the operating system, as well as
periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is clocked by
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