参数资料
型号: SST38VF6401-90-4C-EKE
厂商: SILICON STORAGE TECHNOLOGY INC
元件分类: PROM
英文描述: 4M X 16 FLASH 2.7V PROM, 90 ns, PDSO48
封装: 12 X 20 MM, ROHS COMPLIANT, MO-142DD, TSOP1-48
文件页数: 28/55页
文件大小: 1547K
代理商: SST38VF6401-90-4C-EKE
34
Preliminary Specification
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
2008 Silicon Storage Technology, Inc.
S71309-03-000
08/08
FIGURE 13: WE# Controlled Chip-Erase Timing Diagram
FIGURE 14: WE# Controlled Block-Erase Timing Diagram
1309 F08.1
ADDRESS AMS-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
555
2AA
555
XX55
XX10
XX55
XXAA
XX80
XXAA
555
OE#
CE#
RY/BY#
TWP
SIX-BYTE CODE FOR CHIP-ERASE
TSCE
TBUSY
Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 22)
AMS = Most significant address
AMS = A21 for SST38VF6401/6402/6403/6404
WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence.
X can be VIL or VIH, but no other value.
1309 F09.1
ADDRESS AMS-0
DQ15-0
WE#
SW0
SW1
SW2
SW3
SW4
SW5
555
2AA
555
XX55
XX30
XX55
XXAA
XX80
XXAA
BAX
OE#
CE#
TBusy
RY/BY#
TBE
SIX-BYTE CODE FOR BLOCK-ERASE
TWP
Note: This device also supports CE# controlled Block-Erase operation The WE#
and CE# signals are interchangeable as long as minimum timings are met. (See Table 22)
BAX = Block Address
AMS = Most significant address
AMS = A21 for SST38VF6401/6402/6403/6404
WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence.
X can be VIL or VIH, but no other value.
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