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| 型号： | SST38VF6401-90-4C-EKE |
| 厂商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分类： | PROM |
| 英文描述： | 4M X 16 FLASH 2.7V PROM, 90 ns, PDSO48 |
| 封装： | 12 X 20 MM, ROHS COMPLIANT, MO-142DD, TSOP1-48 |
| 文件页数： | 52/55页 |
| 文件大小： | 1547K |
| 代理商： | SST38VF6401-90-4C-EKE |
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6
Preliminary Specification
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
2008 Silicon Storage Technology, Inc.
S71309-03-000
08/08
Data Protection
The SST38VF6401/6402/6403/6404 provide both hard-
ware and software features to protect nonvolatile data from
inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST38VF6402 and SST39VF6404 devices support
top hardware block protection, which protects the top boot
block of the device. For SST38VF6402, the boot block con-
sists of the top 32 KWord block, and for SST39VF6404 the
boot block consists of the top two 4 KWord sectors
(8 KWord total).
The SST38VF6401 and SST38VF6403 devices support
bottom hardware block protection, which protects the bot-
tom boot block of the device. For SST38VF6401, the boot
block consists of the bottom 32 KWord block, and for
SST39VF6403 the Boot Block consists of the bottom two 4
KWord sectors (8 KWord total). The boot block addresses
are described in Table 2.
Program and Erase operations are prevented on the Boot
Block when WP# is low. If WP# is left floating, it is internally
held high via a pull-up resistor. When WP# is high, the Boot
Block is unprotected, which allows Program and Erase
operations on that area.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
take place. See Figure 20 for more information.
The interrupted Erase or Program operation must be re-ini-
tiated after the device resumes normal operation mode to
ensure data integrity.
Software Data Protection (SDP)
The SST38VF6401/6402/6403/6404 devices implement
the JEDEC approved Software Data Protection (SDP)
scheme for all data alteration operations, such as Program
and Erase. These devices are shipped with the Software
Data Protection permanently enabled. See Table 11 for the
specific software command codes.
All Program operations require the inclusion of the three-
byte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection
from inadvertent Write operations. SDP for Erase opera-
tions is similar to Program, but a six-byte load sequence is
required for Erase operations.
During SDP command sequence, invalid commands will
abort the device to read mode within TRC. The contents of
DQ15-DQ8 can be VIL or VIH, but no other value, during any
SDP command sequence.
The
SST38VF6401/6402/6403/6404
devices
provide
Bypass Mode, which allows for reduced Program and
Erase command sequence lengths. In this mode, the SDP
portion of Program and Erase command sequences are
omitted. See “Bypass Mode” on page 7 for further details.
Common Flash Memory Interface (CFI)
The SST38VF6401/6402/6403/6404 contain Common
Flash Memory Interface (CFI) information that describes
the characteristics of the device. In order to enter the CFI
Query mode, the system can either write a one-byte
sequence using a standard CFI Query Entry command, or
a three-bye sequence using the SST CFI Query Entry
command. A comparison of these two commands is
shown in Table 11. Once the device enters the CFI Query
mode, the system can read CFI data at the addresses
The system must write the CFI Exit command to return to
Read mode. Note that the CFI Exit command is ignored
during an internal Program or Erase operation. See Table
TABLE
2: Boot Block Address Ranges
Product
Size
Address Range
Bottom Boot Uniform
SST38VF6401
32 KW
000000H-007FFFH
Top Boot Uniform
SST38VF6402
32 KW
3F8000H-3FFFFFH
Bottom Boot Non-Uniform
SST38VF6403
8 KW
000000H-001FFFH
Top Boot Non-Uniform
SST38VF6404
8 KW
3FE000H-3FFFFFH
T2.0 1309
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相关代理商/技术参数 |
参数描述 |
|---|---|
| SST38VF6401-90-5C-B3KE | 功能描述:闪存 64M (4Mx16) 90ns 2.7-3.6V Commercial RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST38VF6401-90-5C-EKE | 功能描述:闪存 64M (4Mx16) 90ns 2.7-3.6V Commercial RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST38VF6401-90-5C-EKE-T | 功能描述:闪存 2.7 to 3.6V 64Mbit Parallel Adv MPF+ RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST38VF6401-90-5I-B3KE | 功能描述:闪存 2.7 to 3.6V 64Mbit Parallel Adv MPF+ RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| SST38VF6401-90-5I-B3KE-T | 制造商:Microchip Technology 功能描述:Flash Parallel 3.3V 64Mbit 4M x 16bit 90ns 48-Pin TFBGA T/R 制造商:Microchip Technology Inc 功能描述:2.7V TO 3.6V 64MBIT PM PARALLEL ADVANCED MPF+ - Tape and Reel 制造商:Microchip Technology Inc 功能描述:IC FLASH 64MBIT 90NS 48TFBGA 制造商:Microchip Technology Inc 功能描述:2.7Vto3.6V 64Mb ParAdvanced MPF+ |
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