![](http://datasheet.mmic.net.cn/140000/ST10F252M-4T3_datasheet_5015256/ST10F252M-4T3_198.png)
System reset
ST10F252M
cancelled and the current internal access cycle if any is completed. The external bus cycle
is aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
register was previously set by software. This bit is always cleared on power-on or after a
reset sequence.
Short and long synchronous reset
Once the first maximum 16 TCL are elapsed (4+12 TCL), the internal reset sequence starts.
It is 1024 TCL cycles long. At the end of the sequence and after another 8 TCL, the level of
RSTIN is sampled (after the filter, see RSTF in the drawings). If it is already at high level,
only a short reset is flagged (refer to
Chapter 19 for details on reset flags); if it is recognized
as still low, a long reset is flagged. The major difference between long and short reset is that
during the long reset, P0(15:13) also becomes transparent, so it is possible to change the
clock options.
WARNING:
Warning:
For a short pulse on RSTIN pin and when bidirectional reset
is enabled, the RSTIN pin is held low by the internal circuitry.
At the end of the 1024 TCL cycles, the RTSIN pin is released
but, due to the presence of the input analog filter, the internal
input reset signal (RSTF in the drawings) is released later
(from 50 to 500 ns). This delay is in parallel with the
additional 8 TCL, at the end of which the internal input reset
line (RSTF) is sampled, to decide if the reset event is short or
long. In particular:
The same behavior occurs also when unidirectional reset is
selected and RSTIN pin is held low till the end of the internal
sequence (exactly 1024 TCL + max 16 TCL) and released
exactly at that time.
●
if 8 TCL > 500 ns (FCPU < 8 MHz), the reset event is always recognized as Short
●
if 8 TCL < 500 ns (FCPU > 8MHz), the reset event could be recognized either as Short
or Long, depending on the real filter delay (between 50 and 500 ns) and the CPU
frequency (RSTF sampled high means Short reset, RSTF sampled low means Long
reset). Note that in case a Long reset is recognized, once the 8 TCL are elapsed, the
P0(15:13) pins becomes transparent, so the system clock can be re-configured. The
port returns not transparent 3-4 TCL after the internal RSTF signal becomes high.
The same behavior just described, occurs also when unidirectional reset is selected and
RSTIN pin is held low till the end of the internal sequence (exactly 1024TCL + max 16 TCL)
and released exactly at that time.
Note:
When running with CPU frequency lower than 40 MHz, the minimum valid reset pulse to be
recognized by the CPU (4 TCL) could be longer than the minimum analog filter delay (50ns);
so it might happen that a short reset pulse is not filtered by the analog input filter, but on the
other hand it is not long enough to trigger a CPU reset (shorter than 4 TCL): this would
generate a Flash reset but not a system reset. In this condition, the Flash answers always
with FFFFh, which leads to an illegal opcode and consequently a trap event is generated.