![](http://datasheet.mmic.net.cn/140000/ST10F252M-4T3_datasheet_5015256/ST10F252M-4T3_43.png)
ST10F252M
Multiplier-accumulator unit
6.2.6
40-bit adder/subtracter
The 40-bit adder/subtracter allows intermediate overflows in a series of multiply/accumulate
operations. The adder/subtracter has two input ports. One input is the feedback of the 40-bit
signed accumulator output through the ACCU-shifter.The second input is the 32-bit operand
coming from the one-bit scaler. The 32-bit operands are sign-extended to 40-bit before the
addition/subtraction is performed.
The output of the adder/subtracter goes to the 40-bit signed accumulator. It is also possible
to round and to saturate the result to 32-bit automatically after every accumulation before to
be loaded into the accumulator. The round operation is performed by adding 00’00008000h
to the result. Automatic saturation is enabled by setting the MCW.MS saturation bit.
When the 40-bit signed accumulator is in the overflow saturation mode and an overflow
occurs, the accumulator is loaded with either the most positive or the most negative possible
32-bit value, depending on the direction of the overflow as well as the arithmetic used. The
value of the accumulator upon saturation is 00’7FFF FFFFh (positive) or FF’8000’0000h
(negative).
6.2.7
Data limiter
Saturation arithmetic is also provided to selectively limit overflow, when reading the
accumulator by means of a CoSTORE <destination> MAS instruction. Limiting is performed
on the MAC accumulator. If the contents of the accumulator can be represented in the
destination operand size without overflow, the data limiter is disabled and the operand is not
modified. If the contents of the accumulator cannot be represented without overflow in the
destination operand size, the limiter substitutes a ‘limited’ data as explained in
Table 11’
6.2.8
The accumulator shifter
The accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The
source accumulator shifting operation are:
●
no shift (unmodified)
●
up to 8-bit arithmetic left shift
●
up to 8-bit arithmetic right shift
MSW.ME, MSW.MSV and MSW.MSL bits (see the MSW register description) are affected
by left shifts. Therefore, if the saturation detection is enabled (MCW.MS bit is set), the
behavior is similar to the one of the adder/subtracter.
Table 11.
Limiter output using CoSTORE instruction
ME-flag
MN-flag
MAS value (saturated MAH value)(1)
1.
If the data limiter is activated, a read with “CoSTORE <destination>, <MAH> instruction” or “CoSTORE
<destination>, <MAS> instruction” gives different results.
0
x
Unchanged(2)
2.
When the data limiter is disabled, a reading with “CoSTORE <destination>, <MAH> instruction” or
“CoSTORE <destination>, <MAS> instruction” gives the same result.
10
7FFFh(3)
3.
If the data limiter is activated, a read with “CoSTORE <destination>, <MAH> instruction” or “CoSTORE
<destination>, <MAS> instruction” gives different results.
1
8000h(4)
4.
If the data limiter is activated, a read with “CoSTORE <destination>, <MAH> instruction” or “CoSTORE
<destination>, <MAS> instruction” gives different results.