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参数资料
| 型号： | ST40RA150XH6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA372 |
| 封装： | 27 X 27 MM, BGA-372 |
| 文件页数： | 2/90页 |
| 文件大小： | 672K |
| 代理商： | ST40RA150XH6 |
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ST40RA166
3 Architecture
3.3.3
EMI/MPX interface
The EMI/MPX interface contains the following blocks. For full details of the configuration options of
the EMI please see the
ST40 System Architecture Manual, Volume 2: Bus Interfaces.
EMI memory interface initiator
The EMI provides access to ROMs, SDRAM, memory mapped asynchronous external peripherals
and synchronous MPX bus peripherals. The EMI supports burst mode flash ROM and MPX for
memory-mapped device coupling. The ST40RA166 GPDMA unit accesses external devices and
two sets of DMA channels control signals are provided for this purpose.
EMPI memory interface target
The EMPI is a synchronous MPX target that allows for an external MPX initiator to access the
ST40RA166 internal memory space. The EMPI contains a general purpose control channel and
four high performance channels each of which implements a write buffer and a pair of 32-byte read-
ahead buffers able to optimize external device burst access to and from the ST40RA166 internal
memory. These buffers can be associated with memory regions within the ST40RA166 and external
DMA channels. Four sets of DMA handshake signals are provided to the EMPI to optimize long
burst transfers between the ST40RA166 and external initiators like the STi5514.
MPX bus arbiter
The ST40RA166 has an internal programmable bus arbiter to optimize utilization of the MPX bus.
The ST40RA166 MPX arbiter supports one external initiator and has programmable bus priority
(ST40RA166 or external device), bus parking (ST40RA166, external, idle or last user) and latency
timers. The internal arbiter can be bypassed if an external arbiter supporting more initiators is
required.
3.4
I/O devices
3.4.1
Mailbox
The ST40 and the external microprocessor communicate with each other and synchronize their
activities using the memory-mapped mailbox. Processes generate interrupts to either CPU, and
send and receive messages between the two CPUs. There are buffers for message queueing in
both directions and interrupt bits can be set in each direction. Access to the mailbox from external
devices is through the ST40RA166 EMPI or the PCI target interface.
3.5
Software
3.5.1
Development systems and software
The ST40RA166 supports application development, with a full range of debug features and an
emulation mode (ASE). The ASE mode has a dedicated 1-Kbyte buffer for emulator firmware,
supporting performance counters and branch trace. The ST40RA166, with its memory
management unit, supports standard operating systems including WindowsCE and Linux. The
ST40 has a wide range of development support from ST and third parties, and efficiently runs
applications written in C, C++ and Java.
ST’s own tools include:
q
C/C++ compilers,
q
debugger,
q
proprietary OS.
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST40RA150XHA | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32-bit Embedded SuperH Device |
| ST40RA166 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32-BIT EMBEDDED SUPERH MICROPROCESSOR |
| ST40RA166XH1 | 制造商:STMicroelectronics 功能描述: |
| ST40RA166XH6 | 制造商:STMicroelectronics 功能描述:32-BIT SUPERH CPU - Trays |
| ST40RA166XH6/TR | 制造商:STMicroelectronics 功能描述: |
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