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参数资料
| 型号： | ST40RA150XH6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA372 |
| 封装： | 27 X 27 MM, BGA-372 |
| 文件页数： | 73/90页 |
| 文件大小： | 672K |
| 代理商： | ST40RA150XH6 |
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A Interconnect architecture
ST40RA166
75/88
A.1.5
LMI2 arbiter: (CPU, GPDMA, PCI, EMPI)
The default configuration (after reset) as to be to work fixed priority mode in the following priority
order:
q
PCI,
q
EMPI,
q
GPDMA,
q
CPU buffer (although the CPU requests are not supposed to go in that node to be send in the
LMI, it has to be managed in order to avoid deadlock).
The priority order have to be programmable and the latency checking algorithm can be enabled for
GPDMA, PCI, EMPI.
A.1.6
Return arbitration
The possibilities of the return arbitration are simpler than for the request arbitration. The arbiter is
not programmable but a specific arbitration can be chosen when implementing it.
The arbitration mode chosen is the fixed priority. For each arbiter (one per initiator), the order is the
following: LMI then other targets for the arbiters in node 1 and LMI, EMI, PCI, peripheral subsystem
for the arbiters of node 2.
A.2
Interconnect registers
A summary of registers is given in
Table 36. Addresses in the table are offset from the interconnect
base address at 0x1B05 0000.
Address
offset
Name
Function
0x010
LATENCY
_LMI1_ENABLE
Enables or disables initiators latency counters, see
page 76
0x018
LMI
1_CPU_PRI
Defines priority for the CPU in the LMI1 arbiter, see
page 76
0x020
LATENCY
_LMI1_VALUE
Defines priority and latency value for the node 2 in the LMI1 arbiter, see
page 76
0x110
LATENCY
_LMI2_ENABLE
Enables or disables initiators latency counters, see
page 77
0x118
LMI
2_CPU_PRI
Defines priority for the CPU in the LMI2 arbiter, see
page 77
0x120
LMI
2_LATENCY_PCI
Defines priority and latency value for PCI initiator in the PCI arbiter, see
page 77
0x128
LMI
2_LATENCY_EMPI
Defines priority and latency value for EMPI initiator in the PCI arbiter, see
page 77
0x130
LMI
2_LATENCY_GPDMA
Defines priority and latency value for GPDMA initiator in the PCI arbiter, see
page 77
0x210
LATENCY
_EMI_ENABLE
Enables or disables initiators latency counters, see
page 78
0x218
EMI
_CPU_PRI
Defines priority for the CPU in the EMI arbiter, see
page 78
0x220
EMI
_LATENCY_PCI
Defines priority and latency value for PCI initiator in the EMI arbiter, see
page 78
0x228
EMI
_LATENCY_EMPI
Defines priority and latency value for EMPI initiator in the EMI arbiter, see
page 78
0x230
EMI
_LATENCY_GPDMA
Defines priority and latency value for GPDMA initiator in the EMI arbiter, see
page 79
0x310
LATENCY
_PCI_ENABLE
Enables or disables initiators latency counters, see
page 79
Table 36: Interconnect register summary
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PDF描述 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST40RA150XHA | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32-bit Embedded SuperH Device |
| ST40RA166 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32-BIT EMBEDDED SUPERH MICROPROCESSOR |
| ST40RA166XH1 | 制造商:STMicroelectronics 功能描述: |
| ST40RA166XH6 | 制造商:STMicroelectronics 功能描述:32-BIT SUPERH CPU - Trays |
| ST40RA166XH6/TR | 制造商:STMicroelectronics 功能描述: |
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