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参数资料
| 型号： | ST40RA150XH6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA372 |
| 封装： | 27 X 27 MM, BGA-372 |
| 文件页数： | 89/90页 |
| 文件大小： | 672K |
| 代理商： | ST40RA150XH6 |
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3 Architecture
ST40RA166
9/88
Debug controller
Debugging is performed by break interrupts. There are two break channels. The address, data
value, access type, and data size can all be set as break conditions. Sequential break functions are
supported.
The user debug interface (UDI) contains a five-pin serial interface conforming to JTAG, IEEE
Standard TAP and boundary scan architecture. The interface provides host access to the 1 Kbyte
ASERAM for emulator firmware (accessible only in ASE mode).
Timers
The three-channel, auto-reload, 32-bit timer has an input capture function and a choice of seven
counter input clocks.
Real-time clock
The built-in 32-kHz crystal oscillator has a maximum 1/256 second resolution. It has dynamically
programmable operating frequencies and on-chip clock and calendar functions. It has two sleep
modes and one standby mode.
Programmable PLLs
The ST40RA166 has three programmable PLLs. The PLLs are configured by MODE pins at reset
and then reconfigured by software to optimize system performance or reduce system power
consumption.
General-purpose DMA controller
The five-channel physical address GPDMA controller has four general-purpose channels for
memory-to-memory or memory-to-peripheral transfers, and one buffered multiplexed channel. Both
2-D block moves and linked lists are supported. Two sets of DMA handshake pins are available for
use by external devices to support efficient transfer interdevice transfers via external interfaces such
as the EMI MPX.
Parallel I/O module
24 bits of parallel I/O are provided from the ST40 compatible PIO. Each bit is programmable as an
output or an input. “Input compare” generates an interrupt on any change of any input bit.
3.3
Bus interfaces
3.3.1
Local memory interface
The LMI supports 16-, 32- and 64-bit wide bus SDRAM and DDR SDRAM, at up to 100 MHz with a
maximum address space of 112 Mbytes. Devices supported include two and four bank 16-, 64-,
128- and 256-Mbit technologies in x4, x8, x16 and x32 packages. The LMI pads are dual mode
pads electrically compatible with LVTTL (for standard SDRAM) and SSTL_2 (for DDR SDRAM). For
full detail of the configuration options of the LMI please see
ST40 Architecture Manual, Volume 2:
Bus Interfaces.
3.3.2
PCI interface
The PCI interface complies to the
PCI v2.1 and Power Management Interface V1.0 specifications. It
is 32 bits wide and operates at 33 or 66 MHz. Master and target mode are supported. A PCI arbiter
and clock generator is provided inside the ST40RA166. For details on the configuration options for
the PCI interface please see
ST40 System Architecture Manual, Volume 2: Bus Interfaces.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST40RA150XHA | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32-bit Embedded SuperH Device |
| ST40RA166 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32-BIT EMBEDDED SUPERH MICROPROCESSOR |
| ST40RA166XH1 | 制造商:STMicroelectronics 功能描述: |
| ST40RA166XH6 | 制造商:STMicroelectronics 功能描述:32-BIT SUPERH CPU - Trays |
| ST40RA166XH6/TR | 制造商:STMicroelectronics 功能描述: |
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