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参数资料
| 型号： | ST40RA150XH6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA372 |
| 封装： | 27 X 27 MM, BGA-372 |
| 文件页数： | 21/90页 |
| 文件大小： | 672K |
| 代理商： | ST40RA150XH6 |
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ST40RA166
5 Clock generation
4.8.7
PCI.PERF register definition.
5
Clock generation
The ST40 clock architecture has been organized to maintain compatibility across the ST40 family
and allow additional flexibility to increase system performance where required. It includes a more
diverse range of peripherals and provides low power use.
5.1
Clock domains and sources
Figure 4 shows possible clock domains for ST40RA166 clocks. The ST40RA166 implementation
includes two CLOCKGEN macros, which supply up to three independent clock domains across the
chip
Each PLL may be independently programmed to produce a clock at a specific frequency which is
used to derive a series of related clocks which may be used by the system.
The clock domains mapping is shown in
Table 12. The architecture of the ST40RA166 CLOCKGEN
subsystem consists of two standard (ST40 family) CLOCKGEN units (CLOCKGENA and
PCI.PERF
0x0080
PCI.PERF modifies the function of the PCI.
[3:0]
DLY
_PERRSAMPLE
Parity error delay
Number of app_clock cycles after end of PCI that access master
should wait to see if there is a parity error
RW
4
ENB
_WRITEPOST
Enable write posting in master
RW
5
ENB
_STBYBYPASS
Enable standby bypass
RW
[31:6]
Reserved
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST40RA150XHA | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32-bit Embedded SuperH Device |
| ST40RA166 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:32-BIT EMBEDDED SUPERH MICROPROCESSOR |
| ST40RA166XH1 | 制造商:STMicroelectronics 功能描述: |
| ST40RA166XH6 | 制造商:STMicroelectronics 功能描述:32-BIT SUPERH CPU - Trays |
| ST40RA166XH6/TR | 制造商:STMicroelectronics 功能描述: |
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